Lattice Semiconductor MachXO2 Programming And Configuration Usage Manual page 25

Table 15. Slave SPI Port Pins
Pin Name
CCLK
SI
SO
SN
In the Slave SPI mode, the MCLK/CCLK pin becomes CCLK (i.e. Configuration clock). Input data is read into the
MachXO2 device on the SI pin at the rising edge of CCLK. Output data is valid on the SO pin at the falling edge of
CCLK. The SN acts as the chip select signal. When SN is high, the SSPI interface is deselected and the
SO/SPISO pin is tri-stated. Commands can be written into and data read from the MachXO2 when SN is asserted.
The MachXO2 SSPI port only accepts Mode 0 bus transactions to the Configuration Logic.
Figure 12. Slave SPI Configuration Mode
The SSPI port is active when the MachXO2 is in Feature Row HW Default Mode state (that is, blank/erased). Dia-
mond's default preference for the SLAVE_SPI_PORT is to DISABLE the port. Use the Spreadsheet View to
ENABLE the SLAVE_SPI_PORT preference in your design to keep the SSPI port active in user mode. Lattice rec-
ommends you keep a secondary programming port active in the event the SSPI port is accidentally disabled.
The SSPI port is used to erase, program, and verify the Configuration Flash, User Flash Memory, and the Feature
Row. It is not capable of directly accessing the configuration SRAM. To prevent unintentional erasure of the Feature
Row, it is recommended the SSPI port be used to perform transparent updates of the Flash memory. The SSPI port
can issue a REFRESH command to make a newly programmed image active. The REFRESH command can be
safely used when the MachXO2 is using External or Dual Boot configuration mode because the REFRESH opera-
tion will not begin until SN is deasserted.
Programming the MachXO2 using the SSPI port is complex. Lattice provides 'C' source code called SSPIEmbed-
ded to insulate you from the complexity of programming the MachXO2. It is recommended that SSPIEmbedded be
used when you want to reprogram the MachXO2 Flash memory.
In addition to reprogramming the Flash memory the SSPI port can be used to access several status and control
registers in the MachXO2. A list of the available commands and information about the registers is described in
TN1205, Using User Flash Memory and Hardened Control Functions in MachXO2
registers is less complex and does not require the use of the SSPIEmbedded code.
MachXO2 Programming and Configuration Usage Guide
Configuration clock input that is driven by a SPI master controller.
Serial Data Input to the MachXO2 Configuration Logic for command and data.
Serial Data Output from the MachXO2 configuration logic.
Chip select to enable the MachXO2 configuration logic.
μC
CLK
DI
DO
CSN
Description
MachXO2
Flash Memory
CCLK
SI SPI
Configuration
SO
Controller
Logic
SN
WISHBONE
MachXO2
25
Logic
Devices. Accessing the status