Caen V1495 Technical Information Manual page 4

Document type: Title:
User's Manual (MUT) Mod. V1495 General Purpose VME Board
4.14. USER FPGA F
4.15. USER FPGA C
5. V1495 USER FPGA REFERENCE DESIGN KIT...................................................................................22
5.1. I
NTRODUCTION
5.2. D K ............................................................................................................................................22
ESIGN IT
5.2.1. V1495HAL .....................................................................................................................................22
5.2.2. COIN_REFERENCE Design .........................................................................................................23
5.3. I
NTERFACE DESCRIPTION
5.3.1. Global Signals ...............................................................................................................................25
5.3.2. REGISTER INTERFACE ...............................................................................................................25
5.3.3. V1495 Front Panel Ports (PORT A,B,C,G) INTERFACE.............................................................26
5.3.4. V1495 Mezzanine Expansion Ports (PORT D,E,F) INTERFACE .................................................26
5.3.5. PDL Configuration Interface.........................................................................................................26
5.3.6. Delay Lines and Oscillators I/O ....................................................................................................27
5.3.7. SPARE Interface ............................................................................................................................27
5.3.8. LED Interface ................................................................................................................................27
5.4. R
EFERENCE DESIGN DESCRIPTION
5.5. REGISTER DETAILED DESCRIPTION.............................................................................................31
5.5.1. V1495 Front Panel Ports Registers (PORT A,B,C,G) ...................................................................31
5.5.2. V1495 Mezzanine Expansion Ports Registers (PORT D,E,F) .......................................................32
5.5.3. Delay Selection ..............................................................................................................................32
5.5.4. PDL DELAY VALUE SETTING AND READBACK ......................................................................33
5.5.5. Delay Unit using PDLs..................................................................................................................34
5.5.6. Delay Unit using DLOs .................................................................................................................35
5.6. Q II W
UARTUS
5.7. F
IRMWARE UPGRADE
LIST OF FIGURES
F . 1.1: M . V1495 B
IG OD LOCK
F . 2.1: M V1495
IG ODEL FRONT PANEL
F . 2.2: M
IG ULTIPIN CONNECTOR PIN ASSIGNMENT
F . 2.3: M . A967 C
IG OD ABLE
F . 3.1: T
IG IMERS DIAGRAM
F . 3.2: G
IG ATE PULSE EXAMPLE
F . 3.3: T 2 T
IG IMER AND IMER
F . 3.4: FPGA VME
IG DIAGRAM
F . 3.5: FPGA USER
IG DIAGRAM
F . 4.1: I L
IG NTERRUPT EVEL
F . 4.2: I V
IG NTERRUPT ECTOR
F . 4.3: G
IG EOGRAPHICAL ADDRESS REGISTER
F . 4.4: F R
IG IRMWARE EVISION
NPO:
00117/04:V1495.MUTx/08
M ...........................................................................................................20
LASH EMORY
R
ONFIGURATION EGISTER
.......................................................................................................................................22
........................................................................................................................25
..........................................................................................................27
E P ......................................................................................................36
EB DITION ROJECT
..............................................................................................................................42
D .................................................................................................................7
IAGRAM
( A395A/B/C
WITH
.................................................................................................11
A .................................................................................................................12
DAPTER
....................................................................................................................................14
.............................................................................................................................14
3
USED TOGETHER FOR HANDLING A
.............................................................................................................................15
............................................................................................................................16
R ...................................................................................................................18
EGISTER
R ................................................................................................................19
EGISTER
........................................................................................................19
R ..............................................................................................................19
EGISTER
Filename:
V1495_REV8.DOC
Revision date:
12/02/2010
..........................................................................................21
) ...................................................9
PIGGY BACK BOARDS
G .....................................................15
ATE PULSE
Revision:
8
Number of pages: Page:
42 4