Table 5.7: Coin_Reference Register Map - Caen V1495 Technical Information Manual

Document type: Title:
User's Manual (MUT) Mod. V1495 General Purpose VME Board
The following table illustrates the the register map of the USER FPGA reference design
(COIN_REFERENCE).
NAME
A_STATUS_L
A_STATUS_H
B_STATUS_L
B_STATUS_H
C_STATUS_L
C_STATUS_H
A_MASK_L
A_MASK_H
B_MASK_L
B_MASK_H
C_MASK_L
C_MASK_H
GATEWIDTH
NPO:
00117/04:V1495.MUTx/08

Table 5.7: COIN_REFERENCE register map

ADDRESS DATA SIZING
0x0000 D16
0x0002 D16
0x0004 D16
0x0006 D16
0x0008 D16
0x000A D16
0x000C D16
0x000E D16
0x0010 D16
0x0012 D16
0x0014 D16
0x0016 D16
0x0018 D16
Filename:
V1495_REV8.DOC
Revision date:
12/02/2010
ACCESS NOTES
RO Port A status. This register reflects
A[15:0] bit status.
RO Port A status. This register reflects
A[31:16] bit status.
RO Port B status. This register reflects
B[15:0] bit status.
RO Port B status. This register reflects
B[31:16] bit status.
RO Port C status. This register reflects
C[15:0] bit status.
RO Port C status. This register reflects
C[31:16] bit status.
WO Port A mask. This register masks
A[15:0].
Mask bit is active low.
WO Port A mask. This register masks
A[31:16].
Mask bit is active low.
WO Port B mask. This register masks
B[15:0].
Mask bit is active low.
WO Port B mask. This register masks
B[31:16].
Mask bit is active low.
WO Port C mask. This register masks
C[15:0].
Mask bit is active low.
Port C mask. This register
masks C[31:16].
WO
Mask bit is active low.
WO Gate signal width. This number
represents a multiple
Revision:
8
DEFAULT
X"FFFF"
X"FFFF"
X"FFFF"
X"FFFF"
X"FFFF"
X"FFFF"
X"0004"
of the
Number of pages: Page:
42 29