Interface Description; Global Signals; Register Interface - Caen V1495 Technical Information Manual

Document type: Title:
User's Manual (MUT) Mod. V1495 General Purpose VME Board
PORT NAME
PDL0_IN
PDL1_IN
DLO0_GATE
DLO1_GATE
SPARE_OUT
SPARE_IN
SPARE_DIR
RED_PULSE
GREEN_PULSE

5.3. Interface description

5.3.1.

Global Signals

The nLBRES must be used as an asynchronous reset signal by the user. An active low
pulse will be generated when a write is done at the
§ 4.1).
The LBCLK is a 40 MHz clock. It is the FPGA main clock.
5.3.2.

REGISTER INTERFACE

The signals of the Register Interface allows to read/write into the USER FPGA registers,
which can be accessed via VMEbus. The COIN_REFERENCE module shows how to
implement a set of registers.
The following table shows the registers map as it is provided. Each register address is
coded via constants in V1495pkg.vhd file. This file allows to modify the registers map; all
registers allow D16 accesses (write only, read only or read/write). Registers default value
is the value after a reset for write only and read/write registers; read only registers return
the status of the signals read by the FPGA and have no default value.
The Register Interface allows to abstract the VME registers access. The User can access
a simple register interface: two signals (REG_WREN e REG_RDEN) are pulses with a
one clock cycle duration which enables respectively a write or a read access to a
register. REG_ADDR signal represents the register address.
Writing into a register:
In case of a write operation into a register via VME, the 16 bit datum is available through
the REG_DIN signal. The datum is guaranteed stable on the CLK leading edge where
REG_WREN is active. The register access is valid only when USR_ACCESS is at logic
level = 1.
NPO:
00117/04:V1495.MUTx/08
DIRECTION
OUT 1
OUT 1
OUT 1
OUT 1
SPARE INTERFACE
OUT 12
IN 12
OUT 1
OUT 1
OUT 1
Filename:
V1495_REV8.DOC
Revision date:
12/02/2010
WIDTH
LED INTERFACE
Module Reset register address (see
Revision:
8
DESCRIPTION
Signal to PDL0
Signal to PDL1 Input
Signal to DLO0 Input
Signal to DLO1 Input
SPARE Data Out
SPARE Data In
SPARE Direction
RED Led Pulse (active high)
GREEN Led Pulse (active high)
Number of pages: Page:
42 25