Control Register; Status Register; Interrupt Level Register; Register - Caen V1495 Technical Information Manual

Document type: Title:
User's Manual (MUT) Mod. V1495 General Purpose VME Board
Description
constant1
constant0
c_code
r_code
oui2
oui1
oui0
vers
board2
board1
board0
revis3
revis2
revis1
revis0
sernum1
sernum0
These data are written into one Flash page; at Power ON the Flash content is loaded
into the Configuration ROM.

4.2. Control Register

(Base Address + 0x8000, read/write, D16)
This register allows performing some general settings of the module.
Not used for VME FPGA Rev 0.0. Foreseen for future development

4.3. Status Register

(Base + 0x8002, read only, D16)
This register contains information on the status of the module.
Not used for VME FPGA Rev 0.0. Foreseen for future development

4.4. Interrupt Level Register

(Base Address + 0x8004, read/write, D16)
The 3 LSB of this register contain the value of the interrupt level (Bits 3 to 15 are
meaningless). Default setting is 0x0. In this case interrupt generation is disabled.
Not implemented in VME FPGA Rev 0.0. Available in next releases
NPO:
00117/04:V1495.MUTx/08
Address
0x8114
0x8118
0x811C
0x8120
0x8124
0x8128
0x812C
0x8130
0x8134
0x8138
0x813C
0x8140
0x8144
0x8148
0x814C
0x8180
0x8184
15 14 13 12 11 10 9 8
Fig. 4.1: Interrupt Level Register
Filename:
V1495_REV8.DOC
Revision date:
12/02/2010
Content
0x00
0x40
0xE6
0x00
0x05
0xD7
7 6 5 4 3 2 1 0
LEVEL
Revision:
8
Number of pages: Page:
42 18