CAEN V1724F Manuals

Manuals and User Guides for CAEN V1724F. We have 1 CAEN V1724F manual available for free PDF download: Technical Information Manual

CAEN V1724F Technical Information Manual

CAEN V1724F Technical Information Manual (63 pages)

8 CHANNEL 14 BIT 100 MS/S DIGITIZER

Brand: CAEN | Category: Measuring Instruments | Size: 1 MB

Table of Contents

Table of Contents
3
1 General Description

8
2 Technical Specifications

10
- Packaging
  10
- Power Requirements
  10
- Front Panel
  11
- Fig . 2.1: Mod . V1724 Front Panel
  11
  - External Connectors
    12
    
    ADC REFERENCE CLOCK Connectors
    12
    
    ANALOG INPUT Connectors
    12
    
    CONTROL Connectors
    12
- Fig . 2.2: Amp Clk In/Out Connector
  12
  - Digital I/O Connectors
    13
  - Optical LINK Connector
    13
  - Other Front Panel Components
    13
    
    Displays
    13
  - Internal Components
    13
  - Table 2.2 : Front Panel Leds
    13
- Fig . 2.3: Rotary and Dip Switches Location
  14
  - Technical Specifications Table
    15
  - Table 2.3 : Mod
    15
- Technical Specifications
  15
3 Functional Description

16
- Analog Input
  16
  - Single Ended Input
    16
  - Differential Input
    16
- Fig . 3.1: Single Ended Input Diagram
  16
- Fig . 3.2: Differential Input Diagram
  16
  - Clock Distribution
    17
    
    Direct Drive Mode
    17
- Fig . 3.3: Clock Distribution Diagram
  17
  - PLL Mode
    18
  - Trigger Clock
    18
  - Output Clock
    18
  - AD9510 Programming
    18
  - PLL Programming
    19
  - Direct Drive Programming
    19
  - Configuration File
    19
- Fig . 3.4: Caenpllc Onfig Main Menu
  19
  - Multiboard Synchronisation
    20
  - Internal Clock
    20
  - External Clock and Multiboard Synchronisation
    20
  - Acquisition Modes
    20
    
    Acquisition Run/Stop
    20
    
    Gate and Sample Mode Acquisition
    21
    
    Gate Mode
    21
- Fig . 3.5: Data Storage in Gate Mode
  21
  - Sample Mode
    22
  - Acquisition Triggering: Samples and Events
    22
- Fig . 3.6: Data Storage in Sample Mode
  22
  - Table 3.1: Buffer Organization
    22
  - Custom Size Events
    23
- Fig . 3.7: Trigger Overlap
  23
  - Event Structure
    24
- Event
  24
  - Memory FULL Management
    25
  - Zero Suppression
    25
    
    Full Suppression Based on the Amplitude of the Signal
    25
    
    Full Suppression Based on the Integral of the Signal
    25
    
    Zero Length Encoding ZLE
    25
    
    Zero Suppression Algorithm
    25
- Fig . 3.8: Zero Suppression Example
  26
  - Trigger Management
    30
    
    External Trigger
    30
    
    Software Trigger
    30
- Fig. 3.13: Block Diagram of Trigger Management
  30
  - Local Channel Auto-Trigger
    31
  - Trigger Distribution
    31
  - Front Panel I/Os
    31
- Fig. 3.14: Local Trigger Generation
  31
  - Analog Monitor
    32
    
    Trigger Majority Mode (Monitor Mode = 0)
    32
    
    Analog Monitor/Inspection Mode (Monitor Mode = 2)
    33
    
    Test Mode (Monitor Mode = 1)
    33
- Fig. 3.15: Majority Logic (2 Channels over Threshold; Bit[6] of Ch. Config. Register =0)
  33
- Fig. 3.16: Inspection Mode Diagram
  33
  - Procedure to Enable "Analog Monitor" Mode
    34
  - Applications Examples
    34
- Fig. 3.17: Example of Magnify Parameter Use on Single Channel
  34
  - Buffer Occupancy Mode (Monitor Mode = 3)
    35
  - Voltage Level Mode (Monitor Mode = 4)
    35
- Fig. 3.18: Example of Magnify and Offset Parameters Use on Single Channel
  35
  - Test Pattern Generator
    36
  - Reset, Clear and Default Configuration
    36
    
    Global Reset
    36
    
    Memory Reset
    36
    
    Timer Reset
    36
  - Vmebus Interface
    36
    
    Addressing Capabilities
    36
    
    Base Address
    36
    
    Address Relocation
    37
    
    CR/CSR Address
    37
- Fig. 3.19: A24 Addressing
  37
- Fig. 3.20: A32 Addressing
  37
- Fig. 3.21: CR/CSR Addressing
  37
- Fig. 3.22: Software Relocation of Base Address
  37
  - Data Transfer Capabilities
    38
  - Events Readout
    38
    
    BLOCK TRANSFER D32/D64, 2Evme
    38
    
    Sequential Readout
    38
    
    Single D32
    38
    
    Chained Block Transfer D32/D64
    39
    
    Random Readout (to be Implemented)
    39
- Fig. 3.23: Example of BLT Readout
  39
  - Event Polling
    40
  - Optical Link
    40
- Fig. 3.24: Example of Random Readout
  40
  - Caenvme_Init
    41
  - Caenvme_End
    41
- Fig. 3.25: Optical Link Daisy Chain
  41
  - Caenvme_Readcycle
    42
  - Caenvme_Writecycle
    42
  - Caenvme_Multiread
    42
  - Caenvme_Multiwrite
    43
  - Caenvme_Bltreadcycle
    43
  - Caenvme_Fifobltreadcycle
    44
  - Caenvme_Mbltreadcycle
    44
  - Caenvme_Fifombltreadcycle
    44
  - Caenvme_Irqcheck
    45
  - Caenvme_Irqenable
    45
  - Caenvme_Irqdisable
    45
  - Caenvme_Irqwait
    46
4 Vme Interface

47
- Registers Address Map
  47
- Front
  47
5 Installation

61
- Power on Sequence
  61
- Power on Status
  61
- Firmware Upgrade
  61
  - V1724 Upgrade Files Description
    62

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