Vme Interface; Register Address Map; Configuration Rom; Table 4.1: Address Map For The Model V1495 - Caen V1495 Technical Information Manual

Document type: Title:
User's Manual (MUT) Mod. V1495 General Purpose VME Board

4. VME Interface

4.1. Register address map

The Address map for the Model V1495 is listed in Table 4.1. All register addresses are
referred to the Base Address of the board, i.e. the addresses reported in the Tables are
the offsets to be added to the board Base Address.
ADDRESS
Base + 0x0000÷0x7FFC
Base + 0x8000
Base + 0x8002
Base + 0x8004
Base + 0x8006
Base + 0x8008
Base + 0x800A
Base + 0x800C
Base + 0x800E
Base + 0x8010
Base + 0x8012
Base + 0x8014
Base + 0x8016
Base + 0x8018
Base + 0x8020
Base + 0x8100÷0x801FE
(*)
Read/Write capability depends on USER FPGA implementation
(**) See § 5.7
4.1.1.

Configuration ROM

The following registers contain some module's information according to the Table 3.2,
they are D16 accessible (read only):
•
OUI:
•
Version:
•
Board ID:
•
Revision:
•
Serial MSB:
•
Serial LSB:
Description
checksum
checksum_length2
checksum_length1
checksum_length0
constant2
NPO:
00117/04:V1495.MUTx/08

Table 4.1: Address Map for the Model V1495

REGISTER/CONTENT
USER FPGA Access
Control Register
Status Register
Interrupt Level
Interrupt Status-ID
Geo Address_Register
Module Reset
Firmware revision
Select VME FPGA Flash(**)
VME FPGA Flash memory(**)
Select USER FPGA Flash(**)
USER FPGA Flash memory(**)
USER FPGA Configuration(**)
Scratch16
Scratch32
Configuration ROM(**)
manufacturer identifier (IEEE OUI)
purchased version
Board identifier
hardware revision identifier
serial number (MSB)
serial number (LSB)

Table 4.2: ROM Address Map for the Model V1495

Address
0x8100
0x8104
0x8108
0x810C
0x8110
Filename:
V1495_REV8.DOC
Revision date:
12/02/2010
ADDR DATA
A24/A32 D16
A24/A32 D16
A24/A32 D16
A24/A32 D16
A24/A32 D16
A24/A32 D16
A24/A32 D16
A24/A32 D16
A24/A32 D16
A24/A32 D16
A24/A32 D16
A24/A32 D16
A24/A32 D16
A24/A32 D16
A24/A32 D32
A24/A32 D16
.
Content
Number of pages:
42
Revision:
8
Read/Write
R/W (*)
R/W
R
R/W
R/W
R
W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Page:
17