Delay Unit Using Pdls; Fig. 5.4: Delay Unit With Pdls; Fig. 5.5: Pdls Delay Line Timing - Caen V1495 Technical Information Manual

Document type: Title:
User's Manual (MUT) Mod. V1495 General Purpose VME Board
D) updating of PDL1 delay via VMEbus:
GATE WIDTH (USING Delay Line Oscillators)
The GATEWIDTH register can be used to set the gate signal width on the G port (see
Delay Unit using DLOs, see § 5.5.6).
5.5.5.

Delay Unit using PDLs

The following diagram shows the implementation of the DELAY_UNIT using the one of
the two programmable delay lines (PDL) available on the boards.
PDLx_OUT
The pulse width generated using PDLs (Tp) can be adjusted setting the PDL delay using
either on-board dip switches or through register.
NPO:
00117/04:V1495.MUTx/08
Step 1: write 0x7 in the PDL_CONTROL register
Step2: write the delay value in the PDL_DATA register
PDLx
PULSE
GEN.
'1'
PDL_PULSEOUT
STOPDELAY

Fig. 5.4: Delay Unit with PDLs

COINC
PDLx_IN
PDLx_OUT
PDL_PULSEOUT
STARTDELAY
STOPDELAY

Fig. 5.5: PDLs Delay line timing

Filename:
V1495_REV8.DOC
Revision date:
12/02/2010
'1'
D Q
COINC
STARTDELAY
CLK
CLR
D Q
STOPDELAY
CLK
CLR
Tmon
Tp
Revision:
8
PDLx_IN
MONOSTABLE
(360 ns
pulse)
.
Number of pages: Page:
42 34