V1495 Front Panel Ports (Port A,B,C,G) Interface; V1495 Mezzanine Expansion Ports (Port D,E,F) Interface; Pdl Configuration Interface; V1495 Mezzanine - Caen V1495 Technical Information Manual

Document type: Title:
User's Manual (MUT) Mod. V1495 General Purpose VME Board
Reading from a register:
In case of a read operation from a register via VME, the datum to be returned must drive
the REG_DOUT and be stable on the CLK leading edge, where REG_RDEN is active.
The register access is valid only when USR_ACCESS is at logic level = 1.
5.3.3.

V1495 Front Panel Ports (PORT A,B,C,G) INTERFACE

These signals allows to handle the interface with the motherboard ports A, B, C, G.
A_DIN and B_DIN signals show the logic level of A and B ports (32 bit, input only).
The output logic level on port C can be set via C_DOUT signal.
The logic level on port G (LEMO connectors) can be set via G_LEV signal; the direction
via G_DIR, the datum to be written via G_DOUT or to be read via G_DIN.
5.3.4.

V1495 Mezzanine Expansion Ports (PORT D,E,F) INTERFACE

These signals allows to handle the interface with the piggy back board ports D, E, F.
The following table explains the available signals:
Port: Signal:
D D_DIR
D_DIN
D_DOUT
D_ IDCODE Read IDCODE for piggy back identification
D_LEV
E E_DIR
E_DIN
E_DOUT
E_ IDCODE Read IDCODE for piggy back identification
E_LEV
F F_DIR
F_DIN
F_DOUT
F_ IDCODE Read IDCODE for piggy back identification
F_LEV
5.3.5.

PDL Configuration Interface

PDL Configuration Interface signals are as follows:
PDL_WR
PDL_SEL
PDL_READ
PDL_WRITE
PDL_DIR
NPO:
00117/04:V1495.MUTx/08
Table 5.2: V1495 Mezzanine Expansion Ports signals
Function:
Selects direction
Read the logic level
Set the logic level
Set the logic level
Selects direction
Read the logic level
Set the logic level
Set the logic level
Selects direction
Read the logic level
Set the logic level
Set the logic level

Table 5.3: PDL Configuration Interface signals

OUT 1
OUT 1
IN 8
OUT 8
OUT 1
Filename:
V1495_REV8.DOC
Revision date: Revision:
12/02/2010 8
Applies to:
Bidirectional port
Input/Bidirectional
Output/Bidirectional
All
Output/Bidirectional
Bidirectional port
Input/Bidirectional
Output/Bidirectional
All
Output/Bidirectional
Bidirectional port
Input/Bidirectional
Output/Bidirectional
All
Output/Bidirectional
Write Enable
PDL Selection (0=>PDL0, 1=>PDL1)
Read Data
Write Data
Direction (0=>Write, 1=>Read)
Number of pages:
42
Page:
26