V1495 Mezzanine Expansion Ports Registers (Port D,E,F); Delay Selection; Table 5.8: Selection Of The Delay Line - Caen V1495 Technical Information Manual

Document type: Title:
User's Manual (MUT) Mod. V1495 General Purpose VME Board
MASK register associated with G port. Each bit of the input ports (A,B) mask registers
are internally used in a logic AND operation with the corresponding bit of the port, so it is
an active low mask bit. For instance, when A_ MASK _L[0] is set to '0', the A[0] bit is
internally masked (logic '0').
Each bit of the output port (C) mask register is internally used in a logic AND operation
with the corresponding bit of the internal signal, so it is an active low mask bit. For
instance, when C_ MASK _L[0] is set to '0', the C[0] bit is masked (output bit is stuck at
'0').
The x_STATUS_y (x can be A,B,C; y can be L or H) registers can be used to read back
eack port bit. Each status register is split into two 16 bit register (STATUS_L corresponds
to STATUS[15:0], while STATUS_H corresponds to STATUS[31:0]). There is not a
STATUS register associated with G port. The x_STATUS_y register reflects the status of
the unmasked input and output ports.
A control register (C_CONTROL) is available to set the C port when the board is
configured in I/O register mode.
5.5.2.

V1495 Mezzanine Expansion Ports Registers (PORT D,E,F)

The mezzanine expansion ports (D,E,F) can be configured and accessed using a set of
registers:
In this reference design, no mask register is implemented for the expansion ports.
The x_DATA_y (x can be D,E,F; y can be L or H) registers can be used to read back
each port bit. Each status register is split into two 16 bit register (D_DATA_L corresponds
to D[15:0], while D_DATA_H corresponds to D[31:16]). The expansion ports can be
bidirectional. In case the port is configured as an output, the register value set the port
value. In case the port is configured as an input, the register content reflects current port
value.
A x_CONTROL register (x can be D,E,F) is available to set the corresponding port
direction and logic level selection.
5.5.3.

Delay Selection

The selection of the asynchronous timer is made through the MODE register by means of
the DELAY_SEL bit (MODE[1:0]).
The selection of the delay line is made according to the following table:
MODE[1]
0
0
1
1
NPO:
00117/04:V1495.MUTx/08

Table 5.8: Selection of the delay line

MODE[0]
0
1
0
1
Filename:
V1495_REV8.DOC
Revision date: Revision:
12/02/2010 8
DELAY LINE
PDL0
PDL1
DLO0
DLO1
Number of pages:
42
Page:
32