Delay Unit Using Dlos - Caen V1495 Technical Information Manual

Document type: Title:
User's Manual (MUT) Mod. V1495 General Purpose VME Board
When a coincidence occurs (leading edge of COINC signal) the STARTDELAY signal
becomes active (high). STARTDELAY triggers a monostable in order to generate a pulse
with a duration large enough to ensure maximum linearity performance of the. This value
should be more than 320 ns PDL (see 3D3428 component datasheet). The selected
value in the reference design is 360 ns.
The PDL_PULSEOUT internal signal is generated as the logic OR of PDL_IN and
PDL_OUT, so generating a pulse whose width is proportional to the PDL actual delay.
The PDL_PULSEOUT signal falling edge is used to reset the flip-flop state.
The pulse width (Tp) is:
Tp=Tpd+Tpf
Where Tpd is the delay of the selected PDL. (programmable via VME or by on-board dip-
switches, whichever mode is enabled).
Tpf is the delay introduced by the FPGA pad and internal logic.
The maximum pulse width is limited by the PDL maximum delay, in this case.
5.5.6.

Delay Unit using DLOs

The following diagram shows the implementation of the DELAY_UNIT
oscillators based on delay lines (DLO) present on the board.
DLOx_OUT
NPO:
00117/04:V1495.MUTx/08
'1'
D
COINC
CLK
STOPDELAY
PULSE
CLK
Filename:
V1495_REV8.DOC
Revision date:
12/02/2010
DLOx
STARTDELAY
Q
CLR
Q1
nCLR
PULSE_OUT
DELAY COUNTER
Q
Revision:
8
using two
DLOx_GATE
Number of pages: Page:
42 35