Related Manuals for Caen V1495
Summary of Contents for Caen V1495
- Page 1 Technical Information Manual Revision n. 8 12 February 2010 MOD. V1495 GENERAL PURPOSE VME BOARD NPO: 00117/04:V1495.MUTx/08...
- Page 2 CAEN will repair or replace any product within the guarantee period if the Guarantor declares that the product is defective due to workmanship or materials and has not been caused by mishandling, negligence on behalf of the User, accident or any abnormal conditions or operations.
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Page 3: Table Of Contents
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1495 General Purpose VME Board 12/02/2010 TABLE OF CONTENTS GENERAL DESCRIPTION.........................6 1.1..............................6 VERVIEW 1.2............................7 LOCK IAGRAM TECHNICAL SPECIFICATIONS ......................8 2.1...............................8 ACKAGING 2.2..........................8 OWER REQUIREMENTS 2.3..........................8 RONT PANEL DISPLAYS 2.4. - Page 4 5.3.1. Global Signals ..........................25 5.3.2. REGISTER INTERFACE .......................25 5.3.3. V1495 Front Panel Ports (PORT A,B,C,G) INTERFACE.............26 5.3.4. V1495 Mezzanine Expansion Ports (PORT D,E,F) INTERFACE ..........26 5.3.5. PDL Configuration Interface......................26 5.3.6. Delay Lines and Oscillators I/O ....................27 5.3.7. SPARE Interface ..........................27 5.3.8.
- Page 5 Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1495 General Purpose VME Board 12/02/2010 . 4.5: USER FPGA C ....................21 ONFIGURATION EGISTER . 5.1: USER FPGA ........................22 BLOCK DIAGRAM . 5.2: F ....................28 RONT ANEL ORTS NTERFACE IAGRAM .
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Page 6: General Description
FPGA “User” can be also free reprogrammed by the user with own custom logic function (see § 5.1). It is connected as slave to the FPGA “Bridge” via CAEN Local Bus, whose protocol shall be used in order to communicate with the FPGA “Bridge” and thus with the VME bus. -
Page 7: Block Diagram
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1495 General Purpose VME Board 12/02/2010 1.2. Block Diagram LOCAL BRIDGE 16/32/64 bit FPGA 16 bit (VME interface) 8 bit USER PROGRAMMABLE FPGA FLASH USER FPGA µC CONFIG Asyn. Timers Fig. -
Page 8: Technical Specifications
The module is housed in a 6U-high, 1U-wide VME unit. The board is provided the VME P1, and P2 connectors and fits into both VME standard and V430 backplanes. 2.2. Power requirements The power requirements of the modules are as follows: Table 2.1: Model V1495 and mezzanine boards power requirements Power supply V1495 A395A... -
Page 9: Front Panel
Mod. V1495 General Purpose VME Board 12/02/2010 2.4. Front Panel Mod. V560E Mod. V1495 USER DTACK SCALE GENERAL PURPOSE VME BOARD Fig. 2.1: Model V1495 front panel (with piggy back boards) A395A/B/C NPO: Filename: Number of pages: Page: 00117/04:V1495.MUTx/08 V1495_REV8.DOC... -
Page 10: Motherboard Specifications
User's Manual (MUT) Mod. V1495 General Purpose VME Board 12/02/2010 2.5. Motherboard Specifications The Mod. V1495 Motherboard is composed by four I/O sections (see § 1.2), described in the following table: Table 2.2: V1495 Motherboard I/O sections Board No. of Ch. -
Page 11: Mezzanine Boards Installation
User's Manual (MUT) Mod. V1495 General Purpose VME Board 12/02/2010 2.7. Mezzanine boards installation In order to install one A395x-series mezzanine board on the V1495 motherboard it is necessary to follow these steps: − Remove (unscrew) the metal cover (one at will) −... -
Page 12: Fig . 2.3: Mod . A967 Cable Adapter
User's Manual (MUT) Mod. V1495 General Purpose VME Board 12/02/2010 The CAEN Mod. A967 Cable Adapter allows to adapt each Robinson Nugent Multipin Connector into two 1” 17+17-pin Header-type male connectors (3M, 4634-7301) with locks through two 25 cm long flat cables. -
Page 13: Operating Modes
The resulting Gate signal will have stable duration, but with maximum position jitter equal to one clock period. Such position jitter can be rejected by using the asynchronous timers present on the V1495, which allow to generate references synchronous with the occurred trigger. 3.1.1. Timer0, Timer1 Each timer is based on a programmable delay line. -
Page 14: Timer2, Timer3
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1495 General Purpose VME Board 12/02/2010 period width START 0 offset PULSE 0 GATE Tdly= Toffset + Tset Toffset = 30 ± 2ns Tset = SETBINARY * 1ns STARTx-WIDTHMIN = 320ns recommended (22ns absolute min.) -
Page 15: Fpga Programming
The flash related to FPGA VME contains the firmware dedicated to the interface of the board with the FPGA USER and the VME bus; such firmware is developed by CAEN. The flash related to the FPGA USER contains the firmware developed by the User according to his own application requirements. -
Page 16: Fpga User
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1495 General Purpose VME Board 12/02/2010 3.2.2. FPGA USER The microcontroller provides the firmware uploading at board’s power on. The flash memory contains one firmware image only (Standard). FPGA USER Program Circuit... -
Page 17: Vme Interface
4. VME Interface 4.1. Register address map The Address map for the Model V1495 is listed in Table 4.1. All register addresses are referred to the Base Address of the board, i.e. the addresses reported in the Tables are the offsets to be added to the board Base Address. -
Page 18: Control Register
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1495 General Purpose VME Board 12/02/2010 Description Address Content constant1 0x8114 constant0 0x8118 c_code 0x811C r_code 0x8120 oui2 0x8124 0x00 oui1 0x8128 0x40 oui0 0x812C 0xE6 vers 0x8130 board2 0x8134... -
Page 19: Interrupt Status-Id Register
4.5. Interrupt Status-ID Register (Base Address + 0x8006, read/write, D16) This register contains the STATUS/ID that the V1495 places on the VME data bus during the Interrupt Acknowledge cycle (Bits 8 to 15 are meaningless). Default setting is 0xDD. Not implemented in VME FPGA Rev 0.0. Available in next releases... -
Page 20: Scratch16 Register
This register allows the VME FPGA configuration update (stored into on-board flash memory) via VMEBUS. The configuration can be updated by the user by means of the V1495Upgrade software (developed and distributed by CAEN), see § 5.7. 4.12. Select USER FPGA Flash Register (Base Address + 0x8012, read/write, D16) This register allows USER FPGA configuration update (stored into on-board flash memory) via VMEBUS. -
Page 21: User Fpga Configuration Register
Title: Revision date: Revision: User's Manual (MUT) Mod. V1495 General Purpose VME Board 12/02/2010 4.15. USER FPGA Configuration Register (Base Address + 0x8016, read/write, D16) This register allows the update of the USER FPGA configuration. A write access to this register generates a configuration reload. -
Page 22: V1495 User Fpga Reference Design Kit
Fig. 5.1: USER FPGA block diagram 5.2. Design Kit 5.2.1. V1495HAL The V1495 Hardware Abstraction Layer (V1495HAL) is a HDL module provided, in Verilog format at netlist level, in order to help the hardware interfacing. NPO: Filename: Number of pages: Page: 00117/04:V1495.MUTx/08... -
Page 23: Coin_Reference Design
The COIN_REFERENCE design VHDL entity is the interface to the V1495HAL. If the User wishes to use V1495HAL to develop his own application on the V1495 platform, the VHDL entity must not be modified: this means that signals names and function of the COIN_REFERENCE entity must be used, as shown in the following table: Table 5.1: COIN_REFERENCE signals... - Page 24 Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1495 General Purpose VME Board 12/02/2010 PORT NAME DIRECTION WIDTH DESCRIPTION D_DIR D slot Port Direction D_DIN D slot Data In Bus D_DOUT D slot Data Out Bus E_IDCODE E slot mezzanine Identifier...
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Page 25: Interface Description
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1495 General Purpose VME Board 12/02/2010 PORT NAME DIRECTION WIDTH DESCRIPTION PDL0_IN Signal to PDL0 PDL1_IN Signal to PDL1 Input DLO0_GATE Signal to DLO0 Input DLO1_GATE Signal to DLO1 Input... -
Page 26: V1495 Front Panel Ports (Port A,B,C,G) Interface
The register access is valid only when USR_ACCESS is at logic level = 1. 5.3.3. V1495 Front Panel Ports (PORT A,B,C,G) INTERFACE These signals allows to handle the interface with the motherboard ports A, B, C, G. A_DIN and B_DIN signals show the logic level of A and B ports (32 bit, input only). -
Page 27: Delay Lines And Oscillators I/O
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1495 General Purpose VME Board 12/02/2010 5.3.6. Delay Lines and Oscillators I/O Delay Lines and Oscillators signals are as follows (see also § 5.5.5 and § 5.5.6): Table 5.4: Delay Lines and Oscillators signals... -
Page 28: Fig. 5.2: Front Panel Ports Interface Diagram
Revision date: Revision: User's Manual (MUT) Mod. V1495 General Purpose VME Board 12/02/2010 In I/O Register Mode, C port is directly driven by the C_CONTROL register. The coincidence is anyway still active so that a pulse in generated on G port when a coincidence event is detected. -
Page 29: Table 5.7: Coin_Reference Register Map
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1495 General Purpose VME Board 12/02/2010 The following table illustrates the the register map of the USER FPGA reference design (COIN_REFERENCE). Table 5.7: COIN_REFERENCE register map NAME ADDRESS DATA SIZING... - Page 30 Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1495 General Purpose VME Board 12/02/2010 NAME ADDRESS DATA SIZING ACCESS NOTES DEFAULT selected delay line period (see detailed description) C_CONTROL_L 0x001A Port C control. When the port C is X"0000"...
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Page 31: Register Detailed Description
5.5. REGISTER DETAILED DESCRIPTION 5.5.1. V1495 Front Panel Ports Registers (PORT A,B,C,G) The Front Panel ports (A,B,C,G) can be configured and accessed using a set of registers: The x_MASK_y (x can be A,B,C; y can be L or H) registers can be used to selectively mask a bit of a port. -
Page 32: V1495 Mezzanine Expansion Ports Registers (Port D,E,F)
A control register (C_CONTROL) is available to set the C port when the board is configured in I/O register mode. 5.5.2. V1495 Mezzanine Expansion Ports Registers (PORT D,E,F) The mezzanine expansion ports (D,E,F) can be configured and accessed using a set of registers: In this reference design, no mask register is implemented for the expansion ports. -
Page 33: Pdl Delay Value Setting And Readback
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1495 General Purpose VME Board 12/02/2010 5.5.4. PDL DELAY VALUE SETTING AND READBACK The programmable delay lines chip available on board can be programmed with a specific delay using :... -
Page 34: Delay Unit Using Pdls
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1495 General Purpose VME Board 12/02/2010 D) updating of PDL1 delay via VMEbus: Step 1: write 0x7 in the PDL_CONTROL register Step2: write the delay value in the PDL_DATA register... -
Page 35: Delay Unit Using Dlos
Title: Revision date: Revision: User's Manual (MUT) Mod. V1495 General Purpose VME Board 12/02/2010 When a coincidence occurs (leading edge of COINC signal) the STARTDELAY signal becomes active (high). STARTDELAY triggers a monostable in order to generate a pulse with a duration large enough to ensure maximum linearity performance of the. This value should be more than 320 ns PDL (see 3D3428 component datasheet). -
Page 36: Quartus Ii Web Edition Project
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1495 General Purpose VME Board 12/02/2010 Fig. 5.6: Delay Unit with DLOs COINC DLOx_GATE DLOx_OUT PULSE STARTDELAY DELAY_COUNTER STOPDELAY PULSE_OUT Fig. 5.7: DLOs Delay line timing When a coincidence occurs (leading edge of COINC signal) the STARTDELAY signal becomes active (high). -
Page 37: Fig. 5.8: Quartus Ii Project Flow
Title: Revision date: Revision: User's Manual (MUT) Mod. V1495 General Purpose VME Board 12/02/2010 Place&route, starting from the netlist, performs the placing (place) and the subsequent interconnection (route) of the FPGA capabilities. Simulation and timing analysis allow to verify the functionality of the project. The reference design includes a minimum set of contraints in order to allow the design to perform the foreseen function. -
Page 38: Fig. 5.9: Quartus Ii Main Menu
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1495 General Purpose VME Board 12/02/2010 Fig. 5.9: Quartus II main menu Now select File>Open Project… Fig. 5.10: Quartus II file menu NPO: Filename: Number of pages: Page: 00117/04:V1495.MUTx/08 V1495_REV8.DOC... -
Page 39: Fig. 5.11: Quartus Ii Project Browser
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1495 General Purpose VME Board 12/02/2010 browse the file project v1495usr_demo.qpf Fig. 5.11: Quartus II project browser Once the project is open, the Project Navigator shows the following information: There are 5 VHDL files (filename.vhd) and a Verilog netlist (listname.vqm): The reference design is included in the coin_reference.vhd file. -
Page 40: Fig. 5.12: Quartus Ii Netlist
Title: Revision date: Revision: User's Manual (MUT) Mod. V1495 General Purpose VME Board 12/02/2010 Fig. 5.12: Quartus II netlist The first time the project is launched the hierarchy includes only the name of the head of the project (v1495usr_demo). At the end of the project flow the whole hierarchical structure of the project is shown. -
Page 41: Fig. 5.14: Quartus Ii Compiler Launching
Title: Revision date: Revision: User's Manual (MUT) Mod. V1495 General Purpose VME Board 12/02/2010 In order to generate a new programmation file it is necessary to launch the compiler, by clicking on the red “play” button on the tool bar. -
Page 42: Firmware Upgrade
Title: Revision date: Revision: User's Manual (MUT) Mod. V1495 General Purpose VME Board 12/02/2010 5.7. Firmware upgrade It is possible to upgrade the board firmware via VME, by writing the Flash: for this purpose, download the software package and the CVUpgrade tool, both available at: http://www.caen.it/nuclear/software_download.php...