Related Manuals for Caen V2718
Summary of Contents for Caen V2718
- Page 1 Technical Information Manual Revision n. 11 July 03 , 2018 MOD. V2718 VX2718 • VME – PCI OPTICAL LINK BRIDGE MANUAL REV. 11 NPO: 00106/03:V2718.MUTx/11...
- Page 2 The information contained herein has been carefully checked and is believed to be accurate; however, no responsibility is assumed for inaccuracies. CAEN SpA reserves the right to modify its products specifications without giving any notice; for up to date information please visit www.caen.it.
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Page 3: Table Of Contents
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 TABLE OF CONTENTS GENERAL DESCRIPTION ........................... 8 1.1..............................8 VERVIEW 1.2............................. 10 LOCK DIAGRAM 1.3. CONET L ........................... 11 AYOUT VME INTERFACE ............................12 2.1. - Page 4 Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 2.13.26. Display Data High register ......................33 2.13.27. Display Control Left register ......................33 2.13.28. Display Control Right register ....................... 33 2.13.29. Location Monitor Address Low register ..................34 2.13.30.
- Page 5 Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 4.3.10. CAENVME_BLTReadCycle ......................60 4.3.11. CAENVME_MBLTReadCycle ..................... 61 4.3.12. CAENVME_BLTWriteCycle ......................61 4.3.13. CAENVME_MBLTWriteCycle ....................62 4.3.14. CAENVME_ADOCycle ....................... 62 4.3.15. CAENVME_ADOHCycle ......................62 4.3.16.
- Page 6 Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 . 4: V2718 S ........................16 LAVE OPERATION . 5: T ........................17 OCATION ONITOR . 6: S ........................... 21 TATUS EGISTER . 7: C ..........................
- Page 7 Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 1.1: A ..........................9 ABLE VAILABLE ITEMS 1.2: CONET ....................11 ABLE CABLES SPECIFICATIONS 2.1: A V2718 ................... 16 ABLE DDRESS AP FOR THE ODEL 2.2: R...
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Page 8: General Description
1. General description 1.1. Overview The Mod. V2718 is a 1-unit wide 6U VME master module, which can be interfaced to the CONET (Chainable Optical NETwork) and controlled by a standard PC equipped with the PCI card CAEN Mod. A2818 or the PCIe card A3818. The A2818 is a 32-bit 33 MHz PCI... - Page 9 Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 Table 1.1: Available items LED display TTL/NIM I/Os Form factor Code Description V2718KITLC - VME-PCI Bridge VME6U WK2718LCXAAA (V2718) + PCI Optical Link (A2818) +...
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Page 10: Block Diagram
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 1.2. Block diagram V2718 4Mbit FLASH 128K SRAM (FPGA FIRMWARE + BUFFER USER DEFINED) BOOT LOAD FPGA A2719 LOCAL BUS CONET MASTER CONET INTERFACE INTERF. -
Page 11: Conet Layout
30 cm 2 LC Simplex If the network is composed by one A2818, or A3818, and only one V2718, then it is suggested to use X-type cables: such cables have a duplex connector on the A2818 or A3818 side and two simplex connectors on the crate side; the simplex connector with the black wrap is for the RX line and the one with the red wrap is for the TX. -
Page 12: Vme Interface
The V2718 provides all of the addressing and data transfer modes documented in the VME64 specification (except A64 and those intended to improve 3U applications, i.e. A40 and MD32). The V2718 is also compatible with all VME bus modules compliant to pre- VME64 specifications. As VME bus master, the V2718 supports Read-Modify-Write (RMW), and Address-Only-with-Handshake (ADOH) but does not accept RETRY* as a termination from the VME bus slave. -
Page 13: Fair And Demand Request Modes
Requester Type bit in the Control register. In Fair mode, the V2718 does not request the VME bus until there are no other VME bus requests pending at its programmed level. This mode ensures that every requester on an equal level has access to the bus. -
Page 14: Data Transfer Capabilities
IACK: D08, D16, D32 VME Bus Interrupts can be individually masked for each V2718 in the chain. In order to enable the generation of PCI bus interrupts following VME bus interrupts, the IRQEnable function (see § 4.3.48) must be used; then it is necessary to call IRQWait (see §... -
Page 15: Cycle Terminations
The V2718 accepts BERR* or DTACK* as cycle terminations. BERR* is handled as cycle termination whether it is produced by the V2718 itself or by another board. The Status word broadcasted as the cycle is acknowledged, informs the PC HOST about the cycle termination type (BERR* or DTACK*). -
Page 16: Slave
The V2718 can be operated as slave for debugging purposes. It responds to VME cycles (which must be initiated by another master, i.e. a V2718 cannot address itself as a slave) for accessing the Dataway Display internal registers and a Test RAM (32 x 16). The V2718 is accessed both with A32 and A24 base address (see §... -
Page 17: Location Monitor
03/07/2018 2.7. Location Monitor The V2718 monitors the cycles on the bus, whether they are held by itself or by other masters, and produces a Trigger Out LMON signal as soon as a particular cycle is performed (see Fig. 5). The LMON out is available by default as front panel signal. -
Page 18: System Controller Functions
03/07/2018 2.9. System Controller Functions When located in Slot 1 of the VME crate, the V2718 assumes the role of SYSTEM CONTROLLER and sets the SYSTEM CONTROLLER status bit in the STATUS register. In accordance with the VME64 specification, as SYSTEM CONTROLLER the V2718 provides: −... -
Page 19: Iack Daisy Chain Driver
03/07/2018 2.11. IACK Daisy Chain Driver The V2718 can operate as IACK Daisy Chain Driver: it drives low the IACKOUT line of the first slot, thus starting the chain propagation, as soon as it detects an Interrupt Acknowledge cycle by an Interrupt Handler, that could be the V2718 itself. -
Page 20: Internal Registers
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 2.13. Internal registers Table 2.2: Registers map NAME ADDRESS Type Nbit Function STATUS read Status register VME_CTRL read/write VME control register FW_REV read only... -
Page 21: Status Register
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 2.13.1. Status register (Base Address + 0x00, D16, read/write) This register contains information on the status of the module. SYSTEM RESET SYSTEM CONTROL... -
Page 22: Control Register
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 2.13.2. Control register (Base Address + 0x01, D16, read/write) This register allows performing some general settings of the module. ARBITER_TYPE REQUESTER_TYPE RELEASE_TYPE BUS_REQ_LEVEL... -
Page 23: Firmware Download Register
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 2.13.4. Firmware Download register (Base Address + 0x03, D16, read/write) This register is reserved for internal use only. 2.13.5. Flash Enable register (Base Address + 0x04, D16, read/write) This register is reserved for internal use only. -
Page 24: Input Register
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 2.13.8. Input register (Base Address + 0x08, D16, read/write) This register carries the input register pattern. IN0_OR_IN1 PLSA_OUT PLSB_OUT SCR_END_CNT_PLS LMON Fig. 11: Input register 2.13.9. -
Page 25: Output Clear Register
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 2.13.10. Output clear register (Base Address + 0x10, D16, write only) This register allows to clear the output register pattern (1 = Clear, 0 = leave previous setting). -
Page 26: Input Multiplexer Set Register
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 2.13.11. Input Multiplexer Set register (Base Address + 0x0B, D16, read/write) This register allows to set the IN_0 and IN_1 polarity as well as the source of Pulsers/Scaler Signals: 1 = set;... -
Page 27: Input Multiplexer Clear Register
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 2.13.12. Input Multiplexer Clear register (Base Address + 0x11, D16, write only) This register allows to clear the Input Multiplexer settings (1 = Clear, 0 = leave previous setting). -
Page 28: Output Multiplexer Set Register
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 2.13.13. Output Multiplexer Set register (Base Address + 0x0C, D16, read/write) This register allows to set the OUT[4..0] polarity as well as the source of such signals: 1 = set;... -
Page 29: Output Multiplexer Clear Register
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 2.13.14. Output Multiplexer Clear register (Base Address + 0x12, D16, write only) This register allows to clear the Output Multiplexer settings (1 = Clear, 0 = leave previous... -
Page 30: Led Polarity Clear Register
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 2.13.16. LED polarity clear register (Base Address + 0x13, D16, write only) This register allows to clear the LED polarity set via the LED Polarity set register (1 = Clear, 0 = leave previous setting). -
Page 31: Pulser B 0 Register
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 2.13.19. Pulser B 0 register (Base Address + 0x19, D16, read/write) This register allows to set the period and width of the relevant Pulser, measured in range steps (see §... -
Page 32: Scaler 1 Register
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 2.13.22. Scaler 1 register (Base Address + 0x1D, D16, read only) This register allows to monitor the hits accumulated by the Scaler. HITS COUNT Fig. -
Page 33: Display Data High Register
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 2.13.26. Display Data High register (Base Address + 0x23, D16, read only) This register allows to monitor the LED Display Data bits[31..16]. DISP_DATA[31:16] Fig. -
Page 34: Location Monitor Address Low Register
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 2.13.29. Location Monitor Address Low register (Base Address + 0x28, D16, read/write) This register allows to set/monitor the Location monitor Address bits[15..0]; see § 2.7. -
Page 35: Technical Specifications
3. Technical specifications 3.1. Packaging The Model V2718 is a 1-unit wide 6U high VME module. The Mod. A2818 is a 32-bit 33 MHz PCI Bus card The Mod. A3818 is a PCI Express (v1.1 or higher) Bus card compatible with x8 and x16 PCI Express slot. -
Page 36: Front Panel
LINK CONNECTED LED LINK LINK TRANSFER LED TRANSFER LED RX CONNECTOR TX CONNECTOR SYSRES SYSRES PUSHBUTTON PUSHBUTTON SYSRES SYSRES CONET VME CONET VME BRIDGE BRIDGE Fig. 36: Mod. V2718 and A2818/A3818 front panels NPO: Filename: Number of pages: Page: 00106/03:V2718.MUTx/11 V2718_REV11.DOC... -
Page 37: V2718 And A2818/A3818 External Components
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 3.4. V2718 and A2818/A3818 External components 3.4.1. V2718 connectors The location of the connectors is shown in Fig. 3.1. Their electromechanical specifications are listed here below. -
Page 38: V2718 Internal Hardware Components
Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 3.5. V2718 Internal hardware components In the following some hardware setting components, located on the boards, are listed. See Fig. 40 for their exact location on the PCB and their settings. - Page 39 Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 PROG_3 ON BASE ADDRESS LOW [SW8] BASE ADDRESS HIGH [SW9] PROG_3 OFF BASE ADDRESS LOW [SW8] BASE ADDRESS HIGH [SW9] Fig. 37: PROG_3 Switch setting PROG_4: Type: DIP switch.
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Page 40: Internal Jumpers
03/07/2018 3.5.2. Internal jumpers Three jumpers (one on the V2718, one on the A2719 piggy back board and one on the A2818 PCI board) allow to select whether the “Standard” or the “Back up” firmware must be loaded at power on; jumpers’ position is shown in Fig. 38. The A2818 is supplied by the PCI bus;... -
Page 41: Programmable Input/Output
S2 = B, S1 = B -> firmware on page 3 3.6. Programmable Input/Output The V2718 front panel houses 7 LEMO 00 type connectors, 5 outputs and 2 inputs; signals can be either NIM or TTL (dip-switch selectable). Seven green LEDs (one per connector) light up as the relevant signal is active. -
Page 42: Scaler
Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 3.6.2. Scaler It is a counter with the GATE input for enabling the counter and the counter RESET input. The counter has the programmable END_COUNT_LIMIT parameter; LIMIT can be set in the 0 ÷... -
Page 43: I/Ointernal Connections
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 3.7. I/O internal connections LPOL[4] LPOL[3] LPOL[5] LPOL[2] LPOL[6] LPOL[1] IMX[0] LPOL[0] 0 1 2 3 4 5 6 IMX[2] IR[6:0] INPUT0 IN0_OR_IN1... -
Page 44: Vme Dataway Display
RED LED Fig. 40: Dataway Display layout The V2718 is provided with a 88 LED Dataway Display; such LEDs report the VME Bus status (address, data and control lines) related to the latest cycle. ADDR[31:0], AM[5:0], IACK, WRITE and LWORD: These LEDs are frozen on the AS leading edge and remain stable until the next cycle. - Page 45 Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 BRQ: This LED flashes as any Bus Request line (BR[3:0]) is active. SRES: This LED flashes as the SYSRES is active. DTK: This LED turns on if the cycle just executed was terminated with a DTACK asserted by a slave;...
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Page 46: Firmware Upgrade
03/07/2018 3.9. Firmware upgrade The V2718, its A2719 mezzanine board and the A2818 PCI board can store two firmware versions each, called STD and BKP respectively; at Power On, a microcontroller reads the Flash Memory and programs the modules with the firmware version selected via the relevant jumper (see Fig. -
Page 47: Fig . 42: Caenu Pgrader ' S "U
FLASH page to be written. Fig. 42: CAENUpgrader’s “Upgrade Firmware” view The VME “Board number” parameter refers to the position of the V2718 in the CONET network and ranges from 0 to 7, as shown the following picture: Crate side... -
Page 48: Dataway Display
- Use CAENUpgrader to read the firmware revision (in this case the one of the STD copy) so that the board is operative again In case the procedure above also fails, the board needs to be sent back to CAEN in repair (see § 5 for contacts). -
Page 49: V2718 Technical Specifications Table
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 3.10. V2718 technical specifications table Table 3.2: Mod. V2718 technical specifications 1-unit wide and 6U high VME module Packaging Optical Link from PCI / PCIe Bus... -
Page 50: Software Overview
Place the CD in the CD tray in your PC, then the following window will open: Fig. 45: The Software & Documentation Pack CD introduction − Click on “Install CAEN VME Demo” in order to install the provided user friendly interface which allows an easy and immediate control of the module (see § 4.1.3) NPO:... -
Page 51: Hardware Installation
1. The A2818 is a plug-and-play PCI card and must be plugged into one PCI slot (either 5 V or 3.3 V supplied, see § 3.5.2) of the PC motherboard. 2. Connect the TX connector of the A2818 to the RX connector of the first V2718 of the CONET network, via the optical fiber cable. -
Page 52: Caenvme Demo: The Main Menu
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 4.1.3. CAENVME Demo: The Main Menu The Main Menu allows to perform and monitor the supported Data and IRQ cycles. Data cycles: Once the address mode and the data width are selected, the User has to write the address where the cycle must be performed and the eventual datum to be written;... -
Page 53: Software User Interface: I/O Setting Menu - Vme Settings
The VME Settings Menu allows to perform the VME general settings of the V2718; the VME Settings are explained in detail in § 2. Board type must be set to V2718, Link is the PCI slot of the used A2818 (0 to 4) and Board number is the V2718 position in the daisy chain. -
Page 54: Software User Interface: I/O Setting Menu - Scaler
4.1.6. Software User Interface: I/O Setting Menu – Scaler The Scaler Setting Menu allows to perform the settings of the V2718 built in scaler (see § 3.7). The V2718 features an internal scaler, which counts hits arriving on the enabled front panel input (Input_0 or Input_1). -
Page 55: Software User Interface: I/O Setting Menu - Input
Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 4.1.8. Software User Interface: I/O Setting Menu – Input The Input Setting Menu allows to set the polarity of Input_0, Input_1 and of the relevant LEDs see also §... -
Page 56: Software User Interface: I/O Setting Menu - About
The present description refers to CAENVMELib Rel. 1.x, available in the following formats: − Win32 DLL (CAEN provides the CAENVMELib.lib stub for Microsoft Visual C++ 6.0) − Linux dynamic library CAENVMELib is logically located between an application like the samples provided and the device driver. -
Page 57: Caenvme_Init
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 4.3.2. CAENVME_Init Parameters: [in] BdType : The model of the bridge (V2718). [in] Link : The index of the A2818. [in] BdNum : The board number in the link. -
Page 58: Caenvme_Readcycle
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 4.3.5. CAENVME_ReadCycle Parameters: [in] Handle : The handle that identifies the device. [in] Address : The VME bus address. [out] Data : The data read from the VME bus. -
Page 59: Caenvme_Rmwcycle
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 4.3.7. CAENVME_RMWCycle Parameters: [in] Handle: The handle that identifies the device. [in] Address: The VME bus address. [in/out] Data: The data read and then written to the VME bus. -
Page 60: Caenvme_Multiwrite
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 4.3.9. CAENVME_MultiWrite Parameters: [in] Handle : The handle that identifies the device. [in] Address : An array of VME bus addresses. [in] Data : An array of data written to the VME bus. -
Page 61: Caenvme_Mbltreadcycle
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 4.3.11. CAENVME_MBLTReadCycle Parameters: [in] Handle : The handle that identifies the device. [in] Address : The VME bus address. [out] Buffer : The data read from the VME bus. -
Page 62: Caenvme_Mbltwritecycle
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 4.3.13. CAENVME_MBLTWriteCycle Parameters: [in] Handle : The handle that identifies the device. [in] Address : The VME bus address. [in] Buffer : The data to be written to the VME bus. -
Page 63: Caenvme_Setpulserconf
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 4.3.16. CAENVME_SetPulserConf Parameters: [in] Handle : The handle that identifies the device. [in] PulSel : The pulser to configure (see CVPulserSelect enum). [in] Period : The period of the pulse in time units. -
Page 64: Caenvme_Setscalerconf
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 4.3.17. CAENVME_SetScalerConf Parameters: [in] Handle : The handle that identifies the device. [in] Limit : The counter limit for the scaler. [in] AutoReset : Enable/disable the counter auto reset. -
Page 65: Caenvme_Setoutputconf
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 4.3.18. CAENVME_SetOutputConf Parameters: [in] Handle : The handle that identifies the device. [in] OutSel : The ouput line to configure (see CVOutputSelect enum). -
Page 66: Caenvme_Getpulserconf
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 4.3.20. CAENVME_GetPulserConf Parameters: [in] Handle : The handle that identifies the device. [in] PulSel : The pulser to configure (see CVPulserSelect enum). [out] Period : The period of the pulse in time units. -
Page 67: Caenvme_Setoutputconf
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 4.3.22. CAENVME_SetOutputConf Parameters: [in] Handle : The handle that identifies the device. [in] OutSel : The ouput line to configure (see CVOutputSelect enum). -
Page 68: Caenvme_Clearoutputregister
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 4.3.25. CAENVME_ClearOutputRegister Parameters: [in] Handle : The handle that identifies the device. [in] Mask : The lines to be cleared. Returns: An error code about the execution of the function. -
Page 69: Caenvme_Setarbitertype
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 4.3.28. CAENVME_SetArbiterType Parameters: [in] Handle: The handle that identifies the device. [in] Value: The type of VME bus arbitration to implement (see CVArbiterTypes enum). -
Page 70: Caenvme_Setbusreqlevel
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 4.3.31. CAENVME_SetBusReqLevel Parameters: [in] Handle : The handle that identifies the device. [in] Value : The type of VME bus requester priority level to set (see CVBusReqLevels enum). -
Page 71: Caenvme_Getarbitertype
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 4.3.34. CAENVME_GetArbiterType Parameters: [in] Handle : The handle that identifies the device. [out] Value : The type of VME bus arbitration implemented (see CVArbiterTypes enum). -
Page 72: Caenvme_Getbusreqlevel
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 4.3.37. CAENVME_GetBusReqLevel Parameters: [in] Handle : The handle that identifies the device. [out] Value : The type of VME bus requester priority level (see CVBusReqLevels enum). -
Page 73: Caenvme_Systemreset
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 4.3.40. CAENVME_SystemReset Parameters: [in] Handle : The handle that identifies the device. Returns: An error code about the execution of the function. Description: The function performs a system reset on the module. -
Page 74: Caenvme_Disablescalergate
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 4.3.43. CAENVME_DisableScalerGate Parameters: [in] Handle : The handle that identifies the device. Returns: An error code about the execution of the function. Description: The function disables the gate of the scaler. -
Page 75: Caenvme_Iackcycle
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 4.3.46. CAENVME_IACKCycle Parameters: [in] Handle : The handle that identifies the device. [in] Level : The IRQ level to aknowledge (see CVIRQLevels enum). -
Page 76: Caenvme_Irqdisable
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 4.3.49. CAENVME_IRQDisable Parameters: [in] Handle : The handle that identifies the device. [in] Mask : A bit-mask indicating the IRQ lines. Returns: An error code about the execution of the function. -
Page 77: Caenvme_Writeflashpage
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 4.3.52. CAENVME_WriteFlashPage Parameters: [in] Handle : The handle that identifies the device. [in] Data : The data to write. [in] PageNum : The flash page number to write. -
Page 78: Caenvme_Writeregister
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 CAENVME_SetLocationMonitor(long Handle, unsigned long Address, CVAddressModifier Am, short Write,short Lword, short Iack). 4.3.55. CAENVME_WriteRegister Parameters: [in] Handle : The handle that identifies the device. -
Page 79: Technical Support
User's Manual (MUT) Mod. V2718 VME PCI Optical Link Bridge 03/07/2018 5. Technical Support CAEN makes available the technical support of its specialists at the e-mail addresses below: support.nuclear@caen.it (for questions about the hardware) support.computing@caen.it (for questions about software and libraries)