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1
Caen V1495 manual available for free PDF download: Technical Information Manual
Caen V1495 Technical Information Manual (42 pages)
Brand:
Caen
| Category:
Control Unit
| Size: 0.65 MB
Table of Contents
Table of Contents
3
1 General Description
6
Overview
6
Table 1.1: Available Items
6
Block Diagram
7
Fig . 1.1: Mod . V1495 Block Diagram
7
2 Technical Specifications
8
Packaging
8
Power Requirements
8
Front Panel Displays
8
Table 2.1: Model V1495 and Mezzanine Boards Power Requirements
8
Front Panel
9
Fig . 2.1: Model V1495 Front Panel ( with A395A/B/Cpiggy Back Boards )
9
Motherboard Specifications
10
Mezzanine Specifications
10
Table 2.2: V1495 Motherboard I/Osections
10
Table 2.3: V1495 Mezzanine Boards
10
Mezzanine Boards Installation
11
Front Panel Connector Cabling
11
Fig . 2.2: Multipin Connector Pin Assignment
11
Fig . 2.3: Mod . A967 Cable Adapter
12
3 Operating Modes
13
Timers
13
Timer0, Timer1
13
Timer2, Timer3
14
Fig . 3.1: Timers Diagram
14
Fig . 3.2: Gate Pulse Example
14
Fpga Programming
15
Fpga Vme
15
Fig . 3.3: Timer 2 and Timer 3 Used Together for Handling a Gate Pulse
15
Fig . 3.4: Fpga Vme Diagram
15
Fpga User
16
Fig . 3.5: Fpga User Diagram
16
4 Vme Interface
17
Register Address Map
17
Configuration ROM
17
Table 4.1: Address Map for the Model V1495
17
Table 4.2: Rom Address Map for the Model V1495
17
Control Register
18
Status Register
18
Interrupt Level Register
18
Register
18
Interrupt Status-ID Register
19
Geo Address Register
19
Module Reset Register
19
Firmware Revision Register
19
Fig . 4.2: Interrupt Vector Register
19
Fig . 4.3: Geographical Address Register
19
Fig . 4.4: Firmware Revision Register
19
Scratch16 Register
20
Scratch32 Register
20
Select Vme Fpga Flash Register
20
Select User Fpga Flash Register
20
Vme Fpga Flash Memory
20
User Fpga Flash Memory
20
User Fpga Configuration Register
21
Fig. 4.5: USER FPGA Configuration Register
21
5 V1495 User Fpga Reference Design Kit
22
Introduction
22
Design Kit
22
V1495Hal
22
Fig. 5.1: USER FPGA Block Diagram
22
COIN_REFERENCE Design
23
Table 5.1: Coin_Reference Signals
23
Interface Description
25
Global Signals
25
Register Interface
25
V1495 Front Panel Ports (PORT A,B,C,G) INTERFACE
26
V1495 Mezzanine Expansion Ports (PORT D,E,F) INTERFACE
26
PDL Configuration Interface
26
V1495 Mezzanine
26
Table 5.3: Pdl Configuration Interface Signals
26
Delay Lines and Oscillators I/O
27
LED Interface
27
Reference Design Description
27
SPARE Interface
27
Table 5.4: Delay Lines and Oscillators Signals
27
Table 5.5: Spare Interface Signals
27
Table 5.6: Led Interface Signals
27
Fig. 5.2: Front Panel Ports Interface Diagram
28
Table 5.7: Coin_Reference Register Map
29
Register Detailed Description
31
V1495 Front Panel Ports Registers (PORT A,B,C,G)
31
V1495 Mezzanine Expansion Ports Registers (PORT D,E,F)
32
Delay Selection
32
Table 5.8: Selection of the Delay Line
32
Pdl Delay Value Setting and Readback
33
Fig. 5.3: PDL_CONTROL Bit Fields
33
Delay Unit Using Pdls
34
Fig. 5.4: Delay Unit with Pdls
34
Fig. 5.5: Pdls Delay Line Timing
34
Delay Unit Using Dlos
35
Quartus II Web Edition Project
36
Fig. 5.6: Delay Unit with Dlos
36
Fig. 5.7: Dlos Delay Line Timing
36
Fig. 5.8: Quartus II Project Flow
37
Fig. 5.9: Quartus II Main Menu
38
Fig. 5.10: Quartus II File Menu
38
Fig. 5.11: Quartus II Project Browser
39
Fig. 5.12: Quartus II Netlist
40
Fig. 5.13: Quartus II Hierarchical Structure
40
Fig. 5.14: Quartus II Compiler Launching
41
Fig. 5.15: Quartus II Compiling Summary
41
Firmware Upgrade
42
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