Pdl Delay Value Setting And Readback; Fig. 5.3: Pdl_Control Bit Fields - Caen V1495 Technical Information Manual

Document type: Title:
User's Manual (MUT) Mod. V1495 General Purpose VME Board
5.5.4.

PDL DELAY VALUE SETTING AND READBACK

The programmable delay lines chip available on board can be programmed with a
specific delay using :
on-board 8 bit dip-switch (SW6 for Delay 0 and SW5 for Delay1 on motherboard)
via VMEbus
Two registers are available to configure PDLs:
PDL_CONTROL
PDL_DATA
PDL_CONTROL is used to:
Select target PDL for read/write operations
Enable delay update
Select programming mode (via VME register or by on-board switches)
The PDL_CONTROL bit fields are shown in the following figure:
PDL_WR = '1' enables the updating of the PDL delay value: in this way, the delay value
set either via dip switch or via PDL_DATA register is automatically loaded. By setting this
bit to 0, the delay value cannot be changed.
PDL_DIR allows to select the source of data for PDL programming:
0: the selected PDL has as delay value on its parallel programming bus the dip switch
value.
1: the selected PDL has as delay value on its parallel programming bus the PDL_DATA
register 8 LSB
PDL_SEL allows to select one of the PDL's (PDL0 and PDL1) for read/write operations.
PDL_DATA register is used to:
Write the delay value for the next delay update via VMEbus
Read the on-board switch status
Examples:
updating of PDL0 delay via switch: the default value in the PDL_CONTROL allows to
update the delay directly via dip switch just after the board turning ON; each change in
the dip switch status set immediately a new delay value.
The sequence to be followed is:
B) updating of PDL1 delay via switch:
C) updating of PDL0 delay via VMEbus:
NPO:
00117/04:V1495.MUTx/08
15 14 13 12 11 10 9

Fig. 5.3: PDL_CONTROL bit fields

Step 1: write 0x1 in the PDL_CONTROL register
Step2: update the dip switches value
Step 1: write 0x5 in the PDL_CONTROL register
Step 2: update the dip switches value
Step 1: write 0x3 in the PDL_CONTROL register
Step2: write the delay value in the PDL_DATA register
Filename:
V1495_REV8.DOC
8 7 6 5 4 3 2 1 0
Revision date: Revision:
12/02/2010 8
PDL_WR
PDL_DIR
PDL_SEL
Number of pages:
42
Page:
33