Operating Modes; Timers; Timer0, Timer1 - Caen V1495 Technical Information Manual

Document type: Title:
User's Manual (MUT) Mod. V1495 General Purpose VME Board

3. Operating modes

3.1. Timers

Gate/Trigger applications require the production of an output signal with programmable
width (Gate), whenever an input signal (Trigger) occurs.
Gates can be produced in several ways, according to the system set up, which can be
either synchronous or asynchronous.
Synchronous systems:
Input signals are referred to a system clock: they can be sampled by the clock itself and
the output is a gate signal (obtained with a counter) whose width (and delay) is a multiple
of the clock period. If the application requires a width (and delay) of the Gate signal
synchronous but with step resolution higher than the system clock period, this can be
achieved by enabling the PLL in the USER FPGA and enter the reference clock on
channel G0.
Asynchronous systems:
Input signals are not referred to a system clock. As a consequence the gate signal will be
generated without any time reference. It is possible to use the implementation described
above, with the freedom of choosing the clock source between external or 40MHz
internal. The resulting Gate signal will have stable duration, but with maximum position
jitter equal to one clock period.
Such position jitter can be rejected by using the asynchronous timers present on the
V1495, which allow to generate references synchronous with the occurred trigger.
3.1.1.

Timer0, Timer1

Each timer is based on a programmable delay line. FPGA USER drives a STARTx pulse
and, after the programmed delay, it receives the return signal PULSEx. The time
difference between transmission and reception (logic implementation inside the FPGA
USER) can be used to drive a gate signal. The programming of the delay time can be
done manually as binary value either via 8 bit dip switches (SW4 and SW5) or via VME
register, with a 1ns step resolution (max step delay = 255ns). The software setting has
higher priority with respect to the dip switches.
The following figure shows a diagram of the timers usage:
NPO:
00117/04:V1495.MUTx/08
Filename:
V1495_REV8.DOC
Revision date: Revision:
12/02/2010 8
Number of pages:
42
Page:
13