Caen V1495 Technical Information Manual page 30

Document type: Title:
User's Manual (MUT) Mod. V1495 General Purpose VME Board
NAME
C_CONTROL_L
C_CONTROL_H 0x001C
MODE
SCRATCH
G CONTROL
D_CONTROL_L 0x0024
D_CONTROL_H 0x0026
D_DATA_L
D_DATA_H
NPO:
00117/04:V1495.MUTx/08
ADDRESS DATA SIZING
0x001A D16
D16
0x001E D16
0x0020 D16
0x0022 D16
D16
D16
0x0028 D16
0x002A D16
Filename:
V1495_REV8.DOC
Revision date:
12/02/2010
ACCESS NOTES
selected delay line period (see
detailed description)
WO Port C control. When the port C is
configured to be an output under
register control
register), the status of C[15:0] is
controlled by this register.
WO Port C control. When the port C is
configured to be an output under
register control
register), the status of C[31:16] is
controlled by this register.
WO It configures the behaviour of the
system:
MODE[1:0]: DELAY SEL
MODE[3]: UNIT_MODE
'0': Coincidcence Unit
'1': I/O Register
MODE[4]:OPERATOR
'0': C= A AND B;
'1': C = A OR B;
MODE[5]:PULSE_MODE
See Description
RW This register is available to test
read and write to a register.
W Only Bit 0 (G_CONTROL(0)) is
used in this reference design. It can
be used to select G output level:
'0': TTL
'1': NIM
RW
RW
RW
RW
Revision:
8
DEFAULT
X"0000"
(see MODE
X"0000"
(see MODE
X"0008"; --
Default : I/O
Register
Mode.
X"5A5A"
X"0000"
X"0000"
X"0000"
X"0000"
X"0000"
Number of pages: Page:
42 30