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Document type:
Title:
User's Manual (MUT)
Mod. V1495 General Purpose VME Board
5.3.6.
Delay Lines and Oscillators I/O
Delay Lines and Oscillators signals are as follows (see also § 5.5.5 and § 5.5.6):
PDL0_OUT
PDL1_OUT
DLO0_OUT
DLO1_OUT
PDL0_IN
PDL1_IN
DLO0_GATE
DLO1_GATE
5.3.7.
SPARE Interface
These signals allow to set and read the status of SPARE pin present on the board.
SPARE_OUT
SPARE_IN
SPARE_DIR
5.3.8.
LED Interface
These signals, when active for one clock cycle, allow to generate a blink of the relevant
Led.
RED_PULSE
GREEN_PULSE
5.4. Reference design description
The reference design preloaded into the USER FPGA is given as a design guide. It is a
full functional application of the usage of the board as a concidence and/or I/O register
unit. This reference design give access to A,B,C,G ports. So no mezzanine expansion
cards are needed in order to use this design.
The MODE register can be used to set the preferred operating mode. When the board is
switched on, the default operating mode is I/O Register mode.
NPO:
00117/04:V1495.MUTx/08
Table 5.4: Delay Lines and Oscillators signals
IN
1
IN
1
IN
1
IN
1
OUT
1
OUT
1
OUT
1
OUT
1
Table 5.5: SPARE Interface signals
OUT
12
IN
12
OUT
1
Table 5.6: LED Interface signals
OUT
1
OUT
1
Filename:
V1495_REV8.DOC
Revision date:
Revision:
12/02/2010
8
Signal from PDL0 Output
Signal from PDL1 Output
Signal from DLO0 Output
Signal from DLO1 Output
Signal to PDL0
Signal to PDL1 Input
Signal to DLO0 Input
Signal to DLO1 Input
SPARE Data Out
SPARE Data In
SPARE Direction
RED Led Pulse (active high)
GREEN Led Pulse (active high)
Number of pages:
42
Page:
27
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