Quartus Ii Web Edition Project; Fig. 5.6: Delay Unit With Dlos; Fig. 5.7: Dlos Delay Line Timing - Caen V1495 Technical Information Manual

Document type: Title:
User's Manual (MUT) Mod. V1495 General Purpose VME Board
When a coincidence occurs (leading edge of COINC signal) the STARTDELAY signal
becomes active (high).
STARTDELAY enables the oscillator on external delay line (DLOx) selected via MODE
register. At the same time the DELAY_COUNTER is enabled. The PULSE signal leading
edge increases the counter until the value set via GATEWIDTH register is reached. The
PULSE signal corresponds, in this reference, with the selected PDL output. On the first
PULSE leading edge after the coincidence, PULSE_OUT is activated high and is kept
high until a time = GATEWIDTH times the period of the selected DLO. The period in this
case is constant.
The maximum pulse width is limited by the GATEWIDTH counter: in the case of this
reference design the GATEWIDTH register is 16 bit wide, so a maximum width of
65536*Td (Td is the intrinsic delay of the selected DLO).

5.6. Quartus II Web Edition Project

The freely available Altera Quartus II (it can be downloaded from the Altera Web site)
software must be used in order to generate a user firmware for the USER FPGA. It
includes the source of VHDL reference design, which can be modified according to the
decription provided with the manual, in order to modify the card functionalities.
The tool provides a complete pinout of the FPGA; it is also enabled to generate the file
type of programming (RBF format) used fot the flash programming.
This software tool requires the Quartus II Web Edition rel. 5.1 (and newer) and can be
freely downloaded at:
http://www.caen.it/nuclear/software_download.php
Quartus II manual is available at:
The following figure shows the typical project flow for generating the firmware for an
ALTERA FPGA, through the following steps:
Design Entry is the functional descritption of the circuit; it could be either a description of
the hardware (VHDL, Verilog, AHDL) or a scheme made with the tool provide by Quartus.
The reference design provided is developed through VHDL; a VHDL knowledge is
required in order to modify this design. A different description can be developed with a
different language among those allowed by the Quartus tool.
Syntesis translates the descritpion into a format compatible with the subsequent
place&route step.
NPO:
00117/04:V1495.MUTx/08

Fig. 5.6: Delay Unit with DLOs

COINC
DLOx_GATE
DLOx_OUT
PULSE
STARTDELAY
DELAY_COUNTER
STOPDELAY
PULSE_OUT

Fig. 5.7: DLOs Delay line timing

www.altera.com/literature/hb/qts
Filename:
V1495_REV8.DOC
Revision date:
12/02/2010
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Revision:
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Number of pages: Page:
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