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3.
SPECIFICATIONS
M W S S G A
3.3.2
Signal communications
between an
AlSD71
and
each unit
Fig. 3.2 shows a function block diagram for signal communications between
each unit connected to an AlSD71, an AlSCPU, peripheral device, and the
drive unit.
Communication between PC CPU and AlSD71
I
Control signals and data communications via base unit, they consist of:
Control signals
.....
I/O signals given in Section 3.7.
Data
.....................
Written to and read from the buffer memory by the PC
CPU. Detailed in Section 3.5.
Communication between peripheral device (or
AD71TU) and AiSD71
Data write, AlSD71 test, AlSD71 monitor, etc. via the AlSD71's RS-422
connector.
Control signal communication to and from the drive unit and pulse train
output from the AISD71. (For the I/O interface, refer to Section 3.8.)
Communications between drive unit and
AlSD71
A l S C P U
A l S D 7 1
7 -
-
1
-
Y2D
AlSD71 ready
I C
xll
PC ready
Reverse jog start
Forward jog start
Zero return request
Zero return start
Zero return complete
! *
y27, y29
y28, Y2A
x16, x17
y23, y24
xlc,
XID
I
X12,
X13
X14, X15
x 1 8 , x19
Start corn
lete
Y25.
Y26
I---
Interface
with PC
X1E. X1F
Y2B, Y2C
x10
X1A
x1 B
M
code ON
J
I
I -
u-
I
1
/ I
External
inerfaw
I
r
Drive unit ready
Drive unit
Starl
c
Deviation counter clear
Pulse train
c
Control switching signal
Enable signal
External
signal
I
Positioning
data
writdread
4
Fig. 3.2
AlSD71
Function Block Diagram
3 - 7
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