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Parallel Programming Characteristics
Figure 33. Parallel Programming Timing
Data & Contol
(DATA, XA0/1, BS)
RDY/BSY
Table 17. Parallel Programming Characteristics, T
Symbol
Parameter
V
Programming Enable Voltage
PP
I
Programming Enable Current
PP
t
Data and Control Setup before XTAL1 High
DVXH
t
XTAL1 Pulse Width High
XHXL
t
Data and Control Hold after XTAL1 Low
XLDX
t
XTAL1 Low to WR Low
XLWL
t
BS Valid to WR Low
BVWL
t
BS Hold after RDY/BSY High
RHBX
t
WR Pulse Width Low
WLWH
t
WR High to RDY/BSY Low
WHRL
t
WR Low to RDY/BSY High
WLRH
t
XTAL1 Low to OE Low
XLOL
t
OE Low to DATA Valid
OLDV
t
OE High to DATA Tri-stated
OHDZ
t
WR Pulse Width Low for Chip Erase
WLWH_CE
WR Pulse Width Low for Programming the Fuse
t
Bits
WLWH_PFB
Notes:
1. Use t
for Chip Erase and
WLWH_CE
2. If t
is held longer than
WLWH
t
XTAL1
XHXL
t
DVXH
WR
OE
DATA
(1)
(2)
(2)
t
WLWH_PFB
, no RDY/BSY pulse will be seen.
t
WLRH
t
XLWL
t
t
XLDX
BVWL
t
WLWH
t
WHRL
t
XLOL
t
OLDV
= 25°C ± 10%, V
=5V ± 10%
A
CC
Min
11.5
67
67
67
67
67
67
67
0.5
67
5
1.0
for Programming the Fuse Bits.
AT90S1200
t
RHBX
t
WLRH
t
OHDZ
Typ
Max
12.5
250
20
0.7
0.9
20
20
10
15
1.5
1.8
Units
V
µΑ
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ms
ms
41
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