Atmel AT90S1200 Datasheet page 10

Figure 11. The Parallel Instruction Fetches and Instruction Executions
System Clock Ø
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 12 shows the internal timing concept for the register file. In a single clock cycle an ALU operation using two register
operands is executed, and the result is stored back to the destination register.
Figure 12. Single Cycle ALU Operation
System Clock Ø
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
AT90S1200
10
T1 T2
T1 T2
T3 T4
T3 T4