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Parallel Programming
Characteristics
0839I–AVR–06/02
Figure 52. Parallel Programming Timing
XTAL1
t
DVXH
Data & Contol
(DATA, XA0/1, BS)
WR
RDY/BSY
OE
DATA
Table 26. Parallel Programming Characteristics, T
Symbol
Parameter
V
Programming Enable Voltage
PP
I
Programming Enable Current
PP
t
Data and Control Setup before XTAL1 High
DVXH
t
XTAL1 Pulse Width High
XHXL
t
Data and Control Hold after XTAL1 Low
XLDX
t
XTAL1 Low to WR Low
XLWL
t
BS Valid to WR Low
BVWL
t
BS Hold after RDY/BSY High
RHBX
t
WR Pulse Width Low
WLWH
t
WR High to RDY/BSY Low
WHRL
t
WR Low to RDY/BSY High
WLRH
t
XTAL1 Low to OE Low
XLOL
t
OE Low to DATA Valid
OLDV
t
OE High to DATA Tri-stated
OHDZ
t
WR Pulse Width Low for Chip Erase
WLWH_CE
WR Pulse Width Low for Programming the Fuse
t
Bits
WLWH_PFB
Notes:
1. Use t
for chip erase and t
WLWH_CE
2. If t
is held longer than t
WLWH
t
XLWL
t
XHXL
t
t
XLDX
BVWL
t
WLWH
t
XLOL
t
OLDV
= 25°C ± 10%, V
A
(1)
(2)
(2)
for programming the Fuse bits.
WLWH_PFB
, no RDY/BSY pulse will be seen.
WLRH
AT90S2313
t
RHBX
t
WHRL
t
WLRH
t
OHDZ
= 5V ± 10%
CC
Min
Typ
Max
11.5
12.5
250.0
67.0
67.0
67.0
67.0
67.0
67.0
67.0
20.0
0.5
0.7
0.9
67.0
20.0
20.0
5.0
10.0
15.0
1.0
1.5
1.8
Units
V
µA
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ms
ms
67
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