Atmel AT90S1200 Datasheet page 16

Figure 17. Watchdog Reset During Operation
Interrupt Handling
The AT90S1200 has two Interrupt Mask control registers GIMSK - General Interrupt MASK register - at I/O space address
$3B and the TIMSK - Timer/Counter Interrupt MaSK register at I/O address $39.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are disabled. The user
software can set (one) the I-bit to enable interrupts. The I-bit is set (one) when a Return from Interrupt instruction - RETI - is
executed.
When the Program Counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, hard-
ware clears the corresponding flag that generated the interrupt. Some of the interrupt flags can also be cleared by writing a
logic one to the flag bit position(s) to be cleared.
If an interrupt condition occurs when the corresponding interrupt enable bit is cleared (zero), the interrupt flag will be set
and remembered until the interrupt is enabled, or the flag is cleared by software.
If one or more interrupt conditions occur when the global interrupt enable bit is cleared (zero), the corresponding interrupt
flag(s) will be set and remembered until the global interrupt enable bit is set (one), and will be executed by order of priority.
Note that external level interrupt does not have a flag, and will only be remembered for as long as the interrupt condition is
active.
Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from
an interrupt routine. This must be handled by software.
General Interrupt Mask Register - GIMSK
Bit 7
$3B -
Read/Write R
Initial value 0
•
Bit 7 - Res: Reserved bit
This bit is a reserved bit in the AT90S1200 and always read as zero.
•
Bit 6 - INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled.
The Interrupt Sense Control0 bit 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether
the external interrupt is activated on rising or falling edge of the INT0 pin or low level sensed. INT0 can be activated even if
the pin is configured as an output. See also page 17.
•
Bits 5..0 - Res: Reserved bits
These bits are reserved bits in the AT90S1200 and always read as zero.
AT90S1200
16
6 5 4
INT0 - -
R/W R R
0 0 0
3 2 1
- - -
R R R
0 0 0
0
- GIMSK
R
0