Analog Comparator - Atmel AT90S1200 Datasheet

Analog Comparator

The analog comparator compares the input values on the positive input PB0 (AIN0) and the negative input PB1 (AIN1).
When the voltage on the positive input PB0 (AIN0) is higher than the voltage on the negative input PB1 (AIN1), the Analog
Comparator Output, ACO is set (one). The comparator's output can be set to trigger the Analog Comparator interrupt. The
user can select Interrupt triggering on comparator output rise, fall or toggle. A block diagram of the comparator and its sur-
rounding logic is shown in Figure 21.
Figure 21. Analog Comparator Block Diagram
Analog Comparator Control and Status Register - ACSR
Bit 7
$08 ACD
Read/Write R/W
Initial value 0
•
Bit 7 - ACD: Analog Comparator Disable
When this bit is set(one), the power to the analog comparator is switched off. This bit can be set at any time to turn off the
analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog
Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is
changed.
•
Bit 6 - Res: Reserved bit
This bit is a reserved bit in the AT90S1200 and will always read as zero.
•
Bit 5 - ACO: Analog Comparator Output
ACO is directly connected to the comparator output.
•
Bit 4 - ACI: Analog Comparator Interrupt Flag
This bit is set (one) when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog
Comparator Interrupt routine is executed if the ACIE bit is set (one) and the I-bit in SREG is set (one). ACI is cleared by
hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to
the flag. Observe however, that if another bit in this register is modified using the SBI or CBI instruction, ACI will be cleared
if it has become set before the operation.
•
Bit 3 - ACIE: Analog Comparator Interrupt Enable
When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the analog comparator interrupt is activated.
When cleared (zero), the interrupt is disabled.
•
Bit 2 - Res: Reserved bit
This bit is a reserved bit in the AT90S1200 and will always read as zero.
6 5 4
- ACO ACI
R R R/W
0 0 0
3 2 1
ACIE - ACIS1
R/W R R/W
0 0 0
AT90S1200
0
ACIS0 ACSR
R/W
0
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