Eeprom Read/Write Access - Atmel AT90S1200 Datasheet

Table 6. Watchdog Timer Prescale Select
WDP2 WDP1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
Note: The frequency of the watchdog oscillator is voltage dependent as shown in "Typical Characteristics" on page 48.
The WDR - Watchdog Reset - instruction should always be executed before the Watchdog Timer is enabled. This ensures that
the reset period will be in accordance with the Watchdog Timer prescale settings. If the Watchdog Timer is enabled without
reset, the watchdog timer may not start to count from zero.

EEPROM Read/Write Access

The EEPROM access registers are accessible in the I/O space.
The write access time is in the range of 2.5 - 4ms, depending on the V
user software detect when the next byte can be written. If the user code contains code that writes the EEPROM, some pre-
caution must be taken. In heavily filtered power supplies, V
the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. CPU
operation under these conditions is likely cause the program counter to perform unintentional jumps and eventually execute
the EEPROM write code. To secure EEPROM integrity, the user is advised to use an external under-voltage reset circuit in
this case.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to "EEPROM Control
Register - EECR" on page 24 for details on this.
When the EEPROM is read or written, the CPU is halted for two clock cycles before the next instruction is executed.
EEPROM Address Register - EEAR
Bit 7
$1E -
Read/Write R
Initial value 0
•
Bit 7,6 - Res: Reserved bits
These bits are reserved bit in the AT90S1200 and will always read as zero.
•
Bits 5..0 - EEAR5..0: EEPROM Address
The EEPROM Address Register - EEAR5..0 - specifies the EEPROM address in the 64-byte EEPROM space. The
EEPROM data bytes are addressed linearly between 0 and 63.
Number of WDT
WDP0 Oscillator cycles
0 16K cycles
1 32K cycles
0 64K cycles
1 128K cycles
0 256K cycles
1 512K cycles
0 1,024K cycles
1 2,048K cycles
6 5 4
- EEAR5 EEAR4
R R/W R/W
0 0 0
Typical time-out
at V = 3.0V
CC
47 ms
94 ms
0.19 s
0.38 s
0.75 s
1.5 s
3.0 s
6.0 s
voltages. A self-timing function, however, lets the
CC
is likely to rise or fall slowly on power-up/down. This causes
CC
3 2 1
EEAR3 EEAR2 EEAR1
R/W R/W R/W
0 0 0
AT90S1200
Typical time-out
at V = 5.0V
CC
15 ms
30 ms
60 ms
0.12 s
0,24 s
0.49 s
0.97 s
1.9 s
0
EEAR0 EEAR
R/W
0
23