Usb_Refclk24M; Eth_Clk25M; Resets; Zynq Ps Block - Alpha Data ADM-VPX3-9Z2 User Manual

Signal
VIDEO_REFCLK

3.5.8 USB_REFCLK24M

The USB PHY and hub are provided with an independent 24.0MHz reference clock. This clock is asynchronous
to the clocks generated by the Si5338B and is not connected to the Zynq SoC.

3.5.9 ETH_CLK25M

The Ethernet PHYs are provided with an independant 25.0MHz reference clock. This clock is asynchronous to
the clocks generated by the Si5338B and is not connected to the Zynq SoC..

3.6 Resets

The Zynq PS can be reset via the two push button switches, SW1 and SW2.
Switch Reset Type
Power on Reset
SW1
(PS_POR_B pin)
Soft Reset
SW2
(PS_SRST_B pin)

3.7 Zynq PS Block

3.7.1 Boot Modes

PS_MODE3
(SW4-4)
ON
ON
ON
ON
ON
Note: all other possible switch settings are reserved / invalid.

3.7.2 PS Memory Interfaces

The memory devices attached to the PS side of the MPSoC are outlined below.

3.7.2.1 Quad SPI Flash Memory

The ADM-VPX3-9Z2 has two Quad SPI Flash devices, up to 2Gb each. They can be interfaced seperately in x1,
x2,x4 modes or together in x8 mode.
Page 14
Frequency
27MHz
Table 16 : VIDEO_REFCLK Connection
Effect
Clears all logic. Mode pins sampled (i.e. reconfigures hardware). Reboots
MPSoC.
Same as Power on Reset - but does not sample Mode pins (hardware
configuration unchanged).
PS_MODE2 PS_MODE1
(SW4-3) (SW4-2)
ON ON
ON ON
ON OFF
ON OFF
ON ON
Table 18 : Boot Mode Selection
FPGA Input
PS_MIO27 (Bank
501)
Table 17 : Reset Switches
PS_MODE0
(SW4-1)
ON
OFF
ON
OFF
ON
ADM-VPX3-9Z2 User Manual
V1.1 - 16th January 2020
IO Standard
LVCMOS18
Boot Mode
JTAG
Quad SPI (24 bit addressing)
Quad SPI (32 bit addressing)
SD Flash - SD 2.0
eMMC v4.5 at 1.8V
Functional Description
ad-ug-1323_v1_1.pdf
pin
M21