Clock Generation - Atmel ATmega48PV Manual

17.3

Clock Generation

8025I–AVR–02/09
Figure 17-1. USART Block Diagram
Note: 1. Refer to Figure 1-1 on page 2
The Clock Generation logic generates the base clock for the Transmitter and Receiver. The
USART supports four modes of clock operation: Normal asynchronous, Double Speed asyn-
chronous, Master synchronous and Slave synchronous mode. The UMSELn bit in USART
Control and Status Register C (UCSRnC) selects between asynchronous and synchronous
operation. Double Speed (asynchronous mode only) is controlled by the U2Xn found in the
UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction Register
for the XCKn pin (DDR_XCKn) controls whether the clock source is internal (Master mode) or
external (Slave mode). The XCKn pin is only active when using synchronous mode.
ATmega48P/88P/168P/328P
(1)
UBRRn [H:L]
BAUD RATE GENERATOR
UDRn(Transmit)
TRANSMIT SHIFT REGISTER
RECEIVE SHIFT REGISTER
UDRn (Receive)
UCSRnA
and Table 11-9 on page 88
Clock Generator
OSC
SYNC LOGIC
PIN
CONTROL
Transmitter
TX
CONTROL
PARITY
GENERATOR
PIN
CONTROL
Receiver
CLOCK RX
RECOVERY CONTROL
DATA PIN
RECOVERY CONTROL
PARITY
CHECKER
UCSRnB
for USART0 pin placement.
XCKn
TxDn
RxDn
UCSRnC
177