Atmel ATmega48PV Manual page 265

21.9.3 ADCL and ADCH – The ADC Data Register
21.9.3.1 ADLAR = 0
21.9.3.2 ADLAR = 1
21.9.4 ADCSRB – ADC Control and Status Register B
8025I–AVR–02/09
Bit 15
(0x79) –
(0x78) ADC7
7
Read/Write R
R
Initial Value 0
0
Bit 15
(0x79) ADC9
(0x78) ADC1
7
Read/Write R
R
Initial Value 0
0
When an ADC conversion is complete, the result is found in these two registers.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if
the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from
the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result
is right adjusted.
• ADC9:0: ADC Conversion Result
These bits represent the result from the conversion, as detailed in
page 261.
Bit 7
(0x7B) –
Read/Write R
Initial Value 0
• Bit 7, 5:3 – Res: Reserved Bits
These bits are reserved for future use. To ensure compatibility with future devices, these bist
must be written to zero when ADCSRB is written.
• Bit 2:0 – ADTS2:0: ADC Auto Trigger Source
If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger
an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion
will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a trig-
ger source that is cleared to a trigger source that is set, will generate a positive edge on the
ATmega48P/88P/168P/328P
14 13 12
– – –
ADC6 ADC5 ADC4
6 5 4
R R R
R R R
0 0 0
0 0 0
14 13 12
ADC8 ADC7 ADC6
ADC0 – –
6 5 4
R R R
R R R
0 0 0
0 0 0
6 5 4
ACME – –
R/W R R
0 0 0
11 10 9
– – ADC9
ADC3 ADC2 ADC1
3 2 1
R R R
R R R
0 0 0
0 0 0
11 10 9
ADC5 ADC4 ADC3
– – –
3 2 1
R R R
R R R
0 0 0
0 0 0
"ADC Conversion Result" on
3 2 1
– ADTS2 ADTS1
R R/W R/W
0 0 0
8
ADC8 ADCH
ADC0 ADCL
0
R
R
0
0
8
ADC2 ADCH
– ADCL
0
R
R
0
0
0
ADTS0 ADCSRB
R/W
0
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