Multi-Master Bus Systems, Arbitration And Synchronization - Atmel ATmega48PV Manual

19.3.5 Combining Address and Data Packets into a Transmission
Figure 19-6. Typical Data Transmission
Addr MSB
SDA
SCL
1
START
19.4

Multi-master Bus Systems, Arbitration and Synchronization

8025I–AVR–02/09
Figure 19-5. Data Packet Format
Aggregate
SDA
SDA from
Transmitter
SDA from
Receiver
SCL from
Master
SLA+R/W
A transmission basically consists of a START condition, a SLA+R/W, one or more data packets
and a STOP condition. An empty message, consisting of a START followed by a STOP condi-
tion, is illegal. Note that the Wired-ANDing of the SCL line can be used to implement
handshaking between the Master and the Slave. The Slave can extend the SCL low period by
pulling the SCL line low. This is useful if the clock speed set up by the Master is too fast for the
Slave, or the Slave needs extra time for processing between the data transmissions. The Slave
extending the SCL low period will not affect the SCL high period, which is determined by the
Master. As a consequence, the Slave can reduce the TWI data transfer speed by prolonging the
SCL duty cycle.
Figure 19-6 shows a typical data transmission. Note that several data bytes can be transmitted
between the SLA+R/W and the STOP condition, depending on the software protocol imple-
mented by the application software.
Addr LSB R/W
2 7 8
SLA+R/W
The TWI protocol allows bus systems with several masters. Special concerns have been taken
in order to ensure that transmissions will proceed as normal, even if two or more masters initiate
a transmission at the same time. Two problems arise in multi-master systems:
• An algorithm must be implemented allowing only one of the masters to complete the
transmission. All other masters should cease transmission when they discover that they have
lost the selection process. This selection process is called arbitration. When a contending
master discovers that it has lost the arbitration process, it should immediately switch to Slave
mode to check whether it is being addressed by the winning master. The fact that multiple
ATmega48P/88P/168P/328P
Data MSB
1 2
Data Byte
ACK Data MSB
9 1
Data LSB ACK
7 8 9
Data LSB
2 7 8
Data Byte
STOP, REPEATED
START or Next
Data Byte
ACK
9
STOP
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