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M30850T2-EPB User's Manual
1.4 Specifications
Tables 1.5 and 1.6 list the specifications of the M30850T2-EPB.
Table 1.5 M30850T2-EPB specifications (1/2)
Applicable MCUs
Evaluation MCU
Usable mode
Maximum operating frequency*
Applicable power supply
Basic debugging functions
Real-time trace function
Real-time RAM monitor function
Hardware break function
Execution time measurement function
C0 coverage
External trigger input/event output
Expansion emulation memory
Maximum operating frequency
Specifiable areas
Area size
Emulation memory size
Specifiable bank
* Notes on Using This Product
- When the JP1 of the M30850T2-EPBM is set to VCC1>VCC2, the voltage of VCC2 on the user system should be 3.3 V or
more.
- If using a CPU clock of 30 MHz or more when the voltage of VCC1 is higher then that of VCC2, set the SFR area of the
intelligent I/O function to 2-wait (set the PM13 bit to "1") when reading this area.
These precautions only need to be observed when using an emulator, and do not apply for the actual MCU.
REJ10J1005-0200 Rev.2.00 April 1, 2007
M32C/80, 84, 85, 86 and 8A Groups
M30855FHGP
ROM size: 512 KB + 4 KB, RAM size: 24 KB
Single-chip mode
Memory expansion mode
Microprocessor mode
VCC1 = VCC2 = 4.2 to 5.5 V: 32 MHz
VCC1 = VCC2 = 3.0 to 5.5 V: 24 MHz
Dual-power supply specification
(4.8V ≤ VCC1 ≤ 5.2V and 3.3V ≤ VCC2 ≤ VCC1): 32MHz
3.0--5.5 V
- Download
- Software break (max. 64 points)
- Program execution/stop (allows free-run execution supporting software breaks)
- Memory reference/setting (reference/setting C-variables, run-time execution)
- Register reference/setting
- Disassemble display
- C-level debugging, etc.
- 256K-cycle bus information recordable
(Bus, external trigger, time stamp)
- 5 trace modes supported (Break/Before/About/After/Full)
- Can be recorded ON/OFF by events
- 4,096 bytes (256 bytes x16)
- Data/last access result
8 points (Execution address, bus detection, interrupt, external trigger signal)
Time between program start and stop
Maximum/minimum/average execution time and pass count of specified four
zones.
Count clock: Equal to MCU Clock or 16 MHz
8,192 KB (256 KB x 32 blocks)
External trigger input (MCU-dependent-voltage CMOS level x8) or event output
(break x1, event x7)
-
32 MHz 1Φ + 1Φ
Max. 4 areas
Contiguous 256 KB range or contiguous 1 MB range
(mixed setting of 256 KB range and 1 MB range is available)
4 MB for 4 areas
- For area size 256 KB
X0h, X4h, X8h, XCh banks
e.g.) 20 bank, 64 bank, A8 bank, EC bank etc.
- For area size 1 MB
X0h hank
e.g.) 20 bank, 40 bank, 80 bank, A0 bank etc.
1. Outline
Page 17 of 98
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