JVC GY-DV5000U Service Manual page 78

DBCP SCHEMATIC DIAGRAM 2/7
TO FPGA & TG
(1/7, 3/7)
TO FPGA (3/7)
TO ANALOG
VIDEO
(5/7)
FROM Serial
(7/7)
FROM FPGA (7/7)
FROM CN14
(1/7)
TL
TL
FROM FPGA (3/7)
FROM/TO
CAM CPU (6/7)
DV Interface
C
DMA
RESIZER
ENCORDER
R-Y
CAMERA
Process
Over
Sampling
Y
B-Y
DE MUX
TL
TL
TL
4-10 4-10
Y
C
FROM/TO FPGA (3/7)