JVC GY-DV5000U Service Manual page 117

M62366GP-X [MITSUBISHI]
(8bit 12channel D/A converter)
V (VrefL) 1 20 GND Pin No. Symbol
SS
DI Serial data input terminal to input 12-bit long serial data
A 2 19 A 17
03 02
14 D O Terminal to output MSB data of 12-bit shift register
A 04 3 18 A 01
16 CLK Shift clock input terminal.Input signal at DI pin is input to 12-bit
shift register at rise of shift clock pulse
A 4 17 DI
05
15 LD When H-level signal is input to this terminal,the value stored in 12-bit
A 5 16 CLK
06
shift register is loaded in decoder and D-A converter output register
A
18 01
A 6 15 LD
07
19 A
02
2 A
03
A 08 7 14 D O
3 A 04
4 A 05
A 8 13 A
09 012
A
5 06
8-bit D-A converter output terminal
A
6 07
A 9 12 A
010 011
7 A
08
8 A
09
V (VrefU) 10 11 V
DD CC
9 A 010
A
12 011
A
13 012
(TOP VIEW)
11 VCC Power supply terminal
20 GND GND terminal
V D-A converter upper reference voltage input terminal
10 DD
1 V SS D-A converter lower reference voltage input terminal
Block Diagram
GND A A DI CLK LD D
02 01
20 19 18 17 16 15
- + - +
12bit shift register
D 1 2 3 4 5 6 D7 D8 9 10 D11
8 bit D/A 0
D-A
CONVERTER
Ch2 1
Address
8 bit Latch L (8) Decoder
(12) (12)
8 bit Latch L L L L
Ch3 4 5 6 7 8
8 bit D/A
D-A D-A D-A D-A D-A
CONVERTER
- + - + - + - + - + -
- + - + - + - + - +
Buffer
1 2 3 4 5 6
V A A A A A A
SS 03 04 05 06 07
(VrefL)
MK3754D-X [ICS]
(Low Cost 54MHz 3.3 Volt VCXO)
X1 1 8 X2
VDD
2 7 GND
(Top View)
VIN 3 6 CLK
GND 4 5 VDD
Pin Descriptions
VDD
VIN
X1
13.5 MHz
PLL/Clock
Voltage
Pullable
Synthesis
Controlled
Circuitry
Crystal
Crystal
X2
Oscillator
GND
MB3886PFV [FUJITSU]
(2-Channel DC/DC converter)
Function
Block Diagram
A A V
0 012 011 CC
14 13 12 11
- + - +
D-A D-A
12 11
L L
(12)
L L L
9 10
D-A D-A
+ - + - +
- + - + - +
7 8 9 10
A A V
08 09 010 DD
(VrefU)
Block Diagram
Pin Pin Pin
Pin Description
Number Name Type
1 XI Input Crystal connection. Connect to the external pullable crystal.
2 VDD Power Connect to +3.3 V (0.01uf decoupling capacitor recommended).
3 VIN Input Voltage input to VCXO -- 0 to 3.3 V analog input which controls the
oscillation frequency of the VCXO.
4 GND Power Connect to ground.
5 VDD Power Connect to +3.3 V (0.01uf decoupling capacitor recommended).
6 CLK Output 54 MHz clock output.
7 GND Power Connect to ground.
Input Crystal connection. Connect to the external pullable crystal.
8 X2
54 MHz
(TOP VIEW)
PSIG1 : 1 30 : PSIG2
29 : CTL2
CTL1 : 2
ILIM1 : 3 28 : ILIM2
CT : 4 27 : VREF
RT : 5 26 : VCC
SGND : 6 25 : CSCP
CS1 : 7 24 : CS2
−INE1 : 8 23 : −INE2
FB1 : 9 22 : FB2
+INC1 : 10 21 : +INC2
OUT1-1 : 11 20 : OUT1-2
VS1 : 12 19 : VS2
CB1 : 13 18 : CB2
OUT2-1 : 14 17 : OUT2-2
PGND : 15 16 : VB
MM1571JN-X [MITSUMI]
(1.8V Regulator)
5 4
1 2 3
SOT-25A
(TOP VIEW)
1 V
IN
2 GND
3 Cont
4 Noise
5 V
O
MM1572FN-X [MITSUMI] MM1572KN-X [MITSUMI]
(Refer to MM1571JN-X.) (Refer to MM1571JN-X.)
4-49 4-49
Pin description
Pin No. Pin name I/O Description
1 PSIG1 O CH1 protection status output terminal
CH1 control terminal
2 CTL1 I "H" level : CH1 ON state
"L" level : CH1 OFF state and protection status reset
3 ILIM1 I CH1 overcurrent detection resistor connection terminal
4 CT  Triangular waveform oscillation frequency setting capacitor connection terminal
5 RT  Triangular waveform oscillation frequency setting resistor connection terminal
6 SGND  Ground terminal
7 CS1  CH1 soft-start capacitor connection terminal
8 −INE1 I CH1 error amp. inverting input terminal
9 FB1 O CH1 error amp. output terminal
10 +INC1 I CH1 overvoltage comparator noninverting input terminal
11 OUT1-1 O CH1 totem-pole output terminal (External main-side FET gate drive)
12 VS1  CH1 external main-side FET source connection terminal
CH1 boot capacitor connection terminal
13 CB1 
Connect a capacitor between the CB1 and VS1 terminals.
CH1 totem-pole output terminal (External synchronous-rectification-side FET
14 OUT2-1 O
gate drive)
15 PGND  Ground terminal
16 VB O Output circuit bias output terminal
CH2 totem-pole output terminal (External synchronous-rectification-side FET
17 OUT2-2 O
gate drive)
CH2 boot capacitor connection terminal
18 CB2 
Connect a capacitor between the CB2 and VS2 terminals.
19 VS2  CH2 external main-side FET source connection terminal
20 OUT1-2 O CH2 totem-pole output terminal (External main-side FET gate drive)
21 +INC2  CH2 overvoltage comparator noninverting input terminal
22 FB2 O CH2 error amp. output terminal
23 −INE2 I CH2 error amp. inverting input terminal
24 CS2  CH2 soft-start capacitor connection terminal
25 CSCP  Timer-latch short-circuit protection capacitor connection terminal
26 VCC  Reference voltage, control circuit power supply terminal
27 VREF O Reference voltage output terminal
28 ILIM2 I CH2 overcurrent detection resistor connection terminal
CH2 control terminal
29 CTL2 I "H" level : CH2 ON state
"L" level : CH2 OFF state and protection status reset
30 PSIG2 O CH2 protection status output terminal
Block Diagram
V
IN
Cin
1µF
Bias
Cont
Current
Reference Driver
limitter
Thermal
shutdown
GND
Noise
Cn
0.1µF
MM1573AN-X [MITSUMI] MM1573DN-X [MITSUMI]
(Refer to MM1571JN-X.) (Refer to MM1571JN-X.)
V O
Co
1µF