JVC GY-DV5000U Service Manual page 114

BA6865KV [ROHM]
(Motor Driver Controller)
JCY0136-X [ROHM]
(High frequency operational amplifier for DVC)
8 7 6 5
Block diagram
VCC
IN+ 1
+
-
IN– 2
GND 3
OUT 4
1 2 3 4
BU4094BCFV-X [ROHM]
(8-Stage Shift/Store Register)
CXA3582R [SONY]
(Color LCD driver/Timing generator)
BLOCK DIAGRAM
8 VCC
7 CTLIN1
6 CTLIN2
5 DTROUT
4-46
ICS570B-X [ICS]
(Multiplier and Zero Delay Buffer)
Pin Descriptions
Number Name
1 S1
2 VDD
3 GND
4 ICLK
5 FBIN
6 S0
7 CLK
8 CLK/2
Key: CI = clock input, I = input, O = output, P = power supply connection
Block Diagram
ICLK
S1, S0
FBIN
Analog 3V
Analog 12V
Digital 13V
4-46
1 8
S1 CLK/2
7
2
CLK
VDD
(Top View)
3 6
GND S0
4 5
ICLK
FBIN
Type Description
I Select 1 for output clock.
Connect to GND, VDD, or float per decoding table above.
P Connect to +3.3V.
P Connect to ground.
CI Reference clock input.
CI Feedback clock input.
I Select 0 for output clock.
Connect to GND, VDD, or float per decoding table above.
O Clock output per table above.
O Clock output per table above. Low skew divide by two of pin 7 clock.
Voltage
Phase
Output
Controlled
Detector,
Buffer
2
Oscillator
Charge
Pump, and ÷2
Loop Filter
divide by N Output
Buffer
M5216FP-X [MITSUBISHI]
(Dual Op Amp.)
CLK
CLK/2