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CHAPTER 2: POWER SUPPLY AND INITIAL RESET
2.2 Initial Reset
To initialize the S1C63666 circuits, initial reset must be executed. There are two ways of doing this.
(1) External initial reset by the RESET terminal
(2) External initial reset by simultaneous high input to terminals K00–K03 (mask option setting)
The circuits are initialized by either (1) or (2). When the power is turned on, be sure to initialize using the
reset function. It is not guaranteed that the circuits are initialized by only turning the power on.
Figure 2.2.1 shows the configuration of the initial reset circuit.
OSC1
OSC2
Mask option
K00
K01
K02
K03
RESET
V
SS
2.2.1 Reset terminal (RESET)
Initial reset can be executed externally by setting the reset terminal to a high level (V
initial reset is released by setting the reset terminal to a low level (V
The reset input signal is maintained by the RS latch and becomes the internal initial reset signal. The RS
latch is designed to be released by a 2 Hz signal (high) that is divided by the OSC1 clock. Therefore in
normal operation, a maximum of 250 msec (when f
reset is released after the reset terminal goes to low level. Be sure to maintain a reset input of 0.1 msec or
more. However, when turning the power on, the reset terminal should be set at a high level as in the
timing shown in Figure 2.2.1.1.
Note that a reset pulse shorter than 100 nsec is rejected as noise.
The reset terminal should be set to 0.9•V
or more.
After that, a level of 0.5•V
The reset terminal incorporates a pull-down resistor and a mask option is provided to select whether the
resistor is used or not.
12
OSC1
oscillation
circuit
Mask option
Time
authorize
circuit
Fig. 2.2.1 Configuration of initial reset circuit
1.8 V
V
DD
RESET
Power on
Fig. 2.2.1.1 Initial reset at power on
or more (high level) until the supply voltage becomes 1.8 V
DD
or more should be maintained more than 2.0 msec.
DD
1 Hz
Divider
2 Hz
Noise
reject
circuit
R
S
) and the CPU starts operation.
SS
= 32.768 kHz) is needed until the internal initial
OSC1
0.9•V
or more (high level)
DD
0.5•V
DD
2.0 msec or more
EPSON
Internal
initial
reset
Q
). After that the
DD
S1C63666 TECHNICAL MANUAL
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