Epson S1C63666 Technical Manual page 95

Register
Address
D3 D2
PTD13 PTD12 PTD11 PTD10
FFCEH
R
PTD17 PTD16 PTD15 PTD14
FFCFH
R
PTD23 PTD22 PTD21 PTD20
FFD0H
R
PTD27 PTD26 PTD25 PTD24
FFD1H
R
0 EIPT2 EIPT1
FFE1H
R
0 IPT2
FFF1H
R
*1 Initial value at initial reset
*2 Not set in the circuit
CKSEL0: Prescaler 0 source clock selection register (FFC2H•D0)
CKSEL1: Prescaler 1 source clock selection register (FFC2H•D1)
CKSEL2: Prescaler 2 source clock selection register (FFC2H•D2)
Selects the source clock of the prescaler.
When "1" is written: OSC3 clock
When "0" is written: OSC1 clock
Reading: Valid
The source clock for the prescaler is selected from OSC1 or OSC3. When "0" is written to the CKSELx
register, the OSC1 clock is selected as the input clock for the prescaler x (for timer x) and when "1" is
written, the OSC3 clock is selected.
When the event counter mode is selected for timer 0, the setting of CKSEL0 becomes invalid.
When timers 0 and 1 are used as a 16-bit timer, the setting of CKSEL1 becomes invalid.
At initial reset, these registers are set to "0".
PTPS00, PTPS01: Timer 0 prescaler division ratio selection register (FFC3H•D2, D3)
PTPS10, PTPS11: Timer 1 prescaler division ratio selection register (FFC4H•D2, D3)
PTPS20, PTPS21: Timer 2 prescaler division ratio selection register (FFC5H•D2, D3)
Sets the division ratio of the prescaler as shown in Table 4.11.9.2.
When the event counter mode is selected to timer 0, the setting of PTPS00 and PTPS01 becomes invalid.
When timers 0 and 1 are used as a 16-bit timer, the setting of PTPS10 and PTPS11 becomes invalid.
At initial reset, these registers are set to "0".
S1C63666 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
Table 4.11.9.1(b) Control bits of programmable timer
∗1
D1 D0 Name Init
PTD13 0
PTD12 0
PTD11 0
PTD10 0
PTD17 0
PTD16 0
PTD15 0
PTD14 0
PTD23 0
PTD22 0
PTD21 0
PTD20 0
PTD27 0
PTD26 0
PTD25 0
PTD24 0
∗3 ∗2
0 –
EIPT0
EIPT2 0
EIPT1 0
R/W
EIPT0 0
∗3 ∗2
0 –
IPT1 IPT0
IPT2 0
IPT1 0
R/W
IPT0 0
*3 Constantly "0" when being read
Table 4.11.9.2 Selection of prescaler division ratio
PTPSx1 PTPSx0
1
1
0
0
1 0
MSB
Programmable timer 1 data (low-order 4 bits)
LSB
MSB
Programmable timer 1 data (high-order 4 bits)
LSB
MSB
Programmable timer 2 data (low-order 4 bits)
LSB
MSB
Programmable timer 2 data (high-order 4 bits)
LSB
Unused
Enable Mask Interrupt mask register (Programmable timer 2)
Enable Mask
Interrupt mask register (Programmable timer 1)
Enable Mask Interrupt mask register (Programmable timer 0)
(R) (R)
Unused
Yes No Interrupt factor flag (Programmable timer 2)
(W) (W) Interrupt factor flag (Programmable timer 1)
Reset Invalid
Interrupt factor flag (Programmable timer 0)
Prescaler division ratio
1 Source clock / 256
0 Source clock / 32
1 Source clock / 4
0 Source clock / 1
EPSON
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