Epson S1C63666 Technical Manual page 91

The event counter mode also allows use of a noise reject function to eliminate noise such as chattering on
the external clock (K13 input signal). This function is selected by writing "1" to the timer 0 function
selection register FCSEL.
When "with noise rejector" is selected, an input pulse width for both low and high levels must be 0.98
msec∗ or more to count reliably. The noise rejector allows the counter to input the clock at the second
falling edge of the internal 2,048 Hz∗ signal after changing the input level of the K13 input port terminal.
Consequently, the pulse width of noise that can reliably be rejected is 0.48 msec∗ or less.
(∗: f = 32.768 kHz)
OSC1
Figure 4.11.4.2 shows the count down timing with noise rejector.
2,048 Hz ∗
EVIN input (K13)
Counter
input clock ∗
Counter data
The operation of the event counter mode is the same as the normal timer except it uses the K13 input as
the clock. Refer to Section 4.11.2, "Basic count operation" for basic operation and control.
4.11.5 16-bit timer (timer 0 + timer 1)
Timers 0 and 1 can be used as a 16-bit timer.
To use the 16-bit timer, write "1" to the timer 0 16-bit mode selection register MOD16.
The 16-bit timer is configured with timer 0 for low-order byte and timer 1 for high-order byte as shown in
Figure 4.11.5.1.
K13
Timer 0 Run/Stop
PTRUN0
OSC1
f
OSC1
oscillation
Selector
circuit
OSC3
CKSEL0
oscillation
f
OSC3
circuit
Interrupt
TOUT
The registers for timer 0 are used to control the timer. Thus the event counter function can also be used.
Timer 1 operates with the timer 0 underflow signal as the count clock, so the clock and RUN/STOP
control registers for timer 1 become invalid.
The counter data in 16-bit mode must be read in the order below.
PTD00–PTD03 → PTD04–PDT07 → PTD10–PTD13 → PTD14–PTD17
S1C63666 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
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2
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Fig. 4.11.4.2 Count down timing with noise rejector
Timer 0 + Timer 1
Input port
K13
Prescaler
Prescaler
setting
PTPS00
Divider
PTPS01
Timer function setting
FCSEL
PLPOL
Pulse polarity setting
Fig. 4.11.5.1 Configuration of 16-bit timer
n-1
∗
1 When f is 32.768 kHz
OSC1
∗
2 When PLPOL register is set to "0"
Timer 0
Low-order 8 bits
Reload data register
PTRST0
RLD00–RLD07
Timer 0 reset
Clock
8-bit
control
down counter
circuit
Data buffer
PTD00–PTD07
EVCNT
Event counter mode setting
EPSON
n-2 n-3
Timer 1
High-order 8 bits
Reload data register
RLD10–RLD17
8-bit
down counter
Data buffer
PTD10–PTD17
Under-
flow
signal
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