Table of Contents
Advertisement
2.2.2 Simultaneous high input to terminals K00–K03
Another way of executing initial reset externally is to input a high signal simultaneously to the input
ports (K00–K03) selected with the mask option.
Since this initial reset passes through the noise reject circuit, maintain the specified input port terminals at
high level for at least 1.5 msec (when the oscillation frequency f
operation. The noise reject circuit does not operate immediately after turning the power on until the
oscillation circuit starts oscillating. Therefore, maintain the specified input port terminals at high level for
at least 1.5 msec (when the oscillation frequency f
Table 2.2.2.1 shows the combinations of input ports (K00–K03) that can be selected with the mask option.
Table 2.2.2.1 Combinations of input ports
1
Not use
2
K00∗K01
3
K00∗K01∗K02
4
K00∗K01∗K02∗K03
Further, the time authorize circuit mask option is selected when this reset function is selected. The time
authorize circuit checks the input time of the simultaneous high input and performs initial reset if that
time is the defined time (1 to 2 sec) or more.
If using this function, make sure that the specified ports do not go high at the same time during ordinary
operation.
2.2.3 Internal register at initial resetting
Initial reset initializes the CPU as shown in Table 2.2.3.1.
The registers and flags which are not initialized by initial reset should be initialized in the program if
necessary.
In particular, the stack pointers SP1 and SP2 must be set as a pair because all the interrupts including
NMI are masked after initial reset until both the SP1 and SP2 stack pointers are set with software.
When data is written to the EXT register, the E flag is set and the following instruction will be executed in
the extended addressing mode. If an instruction which does not permit extended operation is used as the
following instruction, the operation is not guaranteed. Therefore, do not write data to the EXT register for
initialization only.
Refer to the "S1C63000 Core CPU Manual" for extended addressing and usable instructions.
CPU core
Name
Symbol
Data register A
Data register B
Extension register EXT
EXT
Index register X
Index register Y
Program counter
PC
Stack pointer SP1
SP1
Stack pointer SP2
SP2
Zero flag
Carry flag
Interrupt flag
Extension flag
Queue register
S1C63666 TECHNICAL MANUAL
When, for instance, mask option 4 (K00∗K01∗K02∗K03) is
selected, initial reset is executed when the signals input to the
four ports K00–K03 are all high at the same time. When 2 or 3 is
selected, the initial reset is done when a key entry including a
combination of selected input ports is made.
Table 2.2.3.1 Initial values
Number of bits
Setting value
A
4
Undefined
B
4
Undefined
8
Undefined
X
16
Undefined
Y
16
Undefined
16
0110H
8
Undefined
8
Undefined
Z
1
Undefined
C
1
Undefined
I
1
E
1
Q
16
Undefined
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
is 32.768 kHz) during normal
OSC1
is 32.768 kHz) after oscillation starts.
OSC1
Name
RAM
Display memory
Other peripheral circuits
0
0
EPSON
Peripheral circuits
Number of bits
Setting value
4
4
–
∗ See Section 4.1, "Memory Map".
Undefined
Undefined
∗
13
Advertisement
Table of Contents
