Initial Reset; Reset Terminal (Reset) - Epson S1C63454 Technical Manual

2.2 Initial Reset

To initialize the S1C63454 circuits, initial reset must be executed. There are two ways of doing this.
(1) External initial reset by the RESET terminal
(2) External initial reset by simultaneous low input to terminals K00–K03 (mask option setting)
The circuits are initialized by either (1) or (2). When the power is turned on, be sure to initialize using the
reset function. It is not guaranteed that the circuits are initialized by only turning the power on.
Figure 2.2.1 shows the configuration of the initial reset circuit.
OSC1
oscillation
OSC2
Mask option
V
DD
K00
K01
K02
K03
RESET

2.2.1 Reset terminal (RESET)

Initial reset can be executed externally by setting the reset terminal to a low level (V
initial reset is released by setting the reset terminal to a high level (V
The reset input signal is maintained by the RS latch and becomes the internal initial reset signal. The RS
latch is designed to be released by a 2 Hz signal (high) that is divided by the OSC1 clock. Therefore in
normal operation, a maximum of 250 msec (when f
reset is released after the reset terminal goes to high level. Be sure to maintain a reset input of 0.1 msec or
more.
However, when turning the power on, the reset terminal should be set at a low level as in the timing
shown in Figure 2.2.1.1.
The reset terminal should be set to 0.1•V
more (until the supply voltage becomes 2.2 V or more when the CR oscillation circuit has been selected as
the OSC1 oscillation circuit by mask option).
After that, a level of 0.5•V
S1C63454 TECHNICAL MANUAL
OSC1
circuit
Time
authorize
circuit
V
DD
Fig. 2.2.1 Configuration of initial reset circuit
1.8 (2.2) V
V
DD
RESET
Power on
Fig. 2.2.1.1 Initial reset at power on
or less (low level) until the supply voltage becomes 1.8 V or
DD
or less should be maintained more than 2.0 msec.
DD
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
1 Hz
Divider
2 Hz
Mask option
DD
= 32.768 kHz) is needed until the internal initial
OSC1
2.0 msec or more
0.5•V
DD
0.1•V or less (low level)
DD
EPSON
Noise
reject
circuit
R Q
S
). After that the
SS
) and the CPU starts operation.
Internal
initial
reset
9