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4 INITIAL RESET
Initial reset in the E0C88832/88862 is required in order to initialize circuits. This chapter describes
initial reset factors and the initial settings for internal registers.
4.1 Initial Reset Factors
There are three initial reset factors for the
E0C88832/88862 as shown below.
(1) RESET terminal
(2) Simultaneous LOW level input at input port
terminals K00–K03.
(3) Supply voltage detection (SVD) circuit
Figure 4.1.1 shows the configuration of the initial
reset circuit.
Input port K00
K00
Input port K01
K01
Input port K02
K02
Input port K03
K03
V
RESET
V
V
DD
4.1.1 RESET terminal
Initial reset can be done by executed externally
inputting a LOW level to the RESET terminal.
Be sure to maintain the RESET terminal at LOW
level for the regulation time after the power on to
assure the initial reset.
In addition, be sure to use the RESET terminal for
the first initial reset after the power is turned on.
The RESET terminal is equipped with a pull-up
resistor. You can select whether or not to use by
mask option.
4.1.2 Simultaneous LOW level input at
input port terminals K00–K03
Another way of executing initial reset externally is to
input a LOW level simultaneously to the input ports
(K00–K03) selected by mask option.
Since there is a built-in time authorize circuit, be
sure to maintain the designated input port terminal
at LOW level for two seconds (when the oscillation
frequency f
= 32.768 kHz) or more to perform
OSC1
the initial reset by means of this function.
E0C88832/88862 TECHNICAL MANUAL
Time authorize
DD
DD
Supply voltage detection
(SVD) circuit
Fig. 4.1.1 Configuration of initial reset circuit
The CPU and peripheral circuits are initialized by
means of initial reset factors. When the factor is
canceled, the CPU commences reset exception
processing. (See "E0C88 Core CPU Manual".)
When this occurs, reset exception processing
vectors, Bank 0, 000000H–000001H from program
memory are read out and the program (initializa-
tion routine) which begins at the readout address is
executed.
circuit
Mask option
However, the time authorize circuit is bypassed
during the SLEEP (standby) status and oscillation
stabilization waiting period, and initial reset is
executed immediately after the simultaneous LOW
level input to the designated input ports.
The combination of input ports (K00–K03) that can
be selected by mask option are as follows:
(1) Not use
(2) K00 & K01
(3) K00 & K01 & K02
(4) K00 & K01 & K02 & K03
For instance, if mask option (4) "K00 & K01 & K02
& K03" is selected, initial reset will take place when
the input level at input ports K00–K03 is simultane-
ously LOW.
When using this function, make sure that the
designated input ports do not simultaneously
switch to LOW level while the system is in normal
operation.
EPSON
4 INITIAL RESET
SLEEP status
Oscillation stability waiting signal
Internal initial reset
15
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