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4.5 V LCD panel
1/8, 1/5 or 1/4 duty, 1/3 bias
V
DD
V
C1
V
C2
V
C3
CA
CB
V
SS
3 V LCD panel
1/8, 1/5 or 1/4 duty, 1/3 bias
V
DD
V
C1
V
C2
V
C3
CA
CB
V
SS
Fig. 2.1.5.1 External elements when LCD system voltage regulator is not used
Refer to Section 4.8, "LCD Driver", for control of the LCD drive voltage.
2.1.6 Halver mode and saving power
When the supply voltage V
system voltage circuit can be driven with the V
reducing current consumption during HALT or low-speed operation. At initial reset, the low-speed
operation voltage regulator and LCD system voltage circuit are set in the normal mode using V
necessary switch to the halver mode using software. The halver mode supports only low-speed operation
using the OSC1 clock and cannot be set during high-speed operation using the OSC3 clock. The low-
speed operation voltage regulator and the LCD system voltage circuit can be set to the halver mode
independently. Refer to Section 4.2, "Power Control", for control of the halver mode.
2.1.7 Analog system power supply
The V
and V
power supply terminals are provided only for the R/f converter in order to avoid
DDA
SSA
decreasing the conversion accuracy due to noise. However, the same voltage level as the V
be supplied to the V
DDA
V
= V
, V
= V
DDA
DD
SSA
SS
S1C63666 TECHNICAL MANUAL
C
2
C
4
C
3.0 V
1
C
2
C
3
C
3.0 V
1
is 2.4 V or more, the low-speed operation voltage regulator and LCD
DD
–V
.
SSA
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
3 V LCD panel
1/8, 1/5 or 1/4 duty, 1/2 bias
voltage halved. This status is the halver mode for
DD
EPSON
V
DD
C
2
V
C1
V
C2
V
C3
CA
C
3.0 V
1
CB
V
SS
–V
DD
. When
DD
must
SS
11
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