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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Register
Address
D3
D2
VDC3
VDC2
VDC1
FF00H
R/W
CLKCHG OSCC
FF01H
R/W
0
SVDS2 SVDS1 SVDS0
FF04H
R
R/W
CMPON CMPDT SVDDT SVDON
FF05H
R/W
R
FOUTE SWDIR FOFQ1 FOFQ0
FF06H
R/W
0
0
WDEN WDRST
FF07H
R
R/W
SIK03
SIK02
SIK01
FF20H
R/W
K03
K02
K01
FF21H
R
KCP03 KCP02 KCP01 KCP00
FF22H
R/W
SIK13
SIK12
SIK11
FF24H
R/W
K13
K12
K11
FF25H
R
KCP13 KCP12 KCP11 KCP10
FF26H
R/W
R03HIZ R02HIZ R01HIZ R00HIZ
FF30H
R/W
R03
R02
R01
FF31H
R/W
Remarks
∗1 Initial value at initial reset
∗2 Not set in the circuit
∗3 Constantly "0" when being read
18
Table 4.1.1 (a) I/O memory map (FF00H–FF31H)
∗1
D1
D0
Name Init
VDC3
0
VDC0
VDC2
0
VDC1
0
VDC0
0
CLKCHG
0
0
0
OSCC
0
∗3
∗2
0
–
R
∗3
∗2
0
–
∗3
∗2
0
–
SVDS2
0
SVDS1
0
SVDS0
0
CMPON
0
CMPDT
0
SVDDT
0
R/W
SVDON
0
FOUTE
0
SWDIR
0
FOFQ1
0
FOFQ0
0
∗3
∗2
0
–
∗3
∗2
0
–
WDEN
1
W
∗3
WDRST
Reset
SIK03
0
SIK00
SIK02
0
SIK01
0
SIK00
0
∗2
K03
–
K00
∗2
K02
–
∗2
K01
–
∗2
K00
–
KCP03
1
KCP02
1
KCP01
1
KCP00
1
SIK13
0
SIK10
SIK12
0
SIK11
0
SIK10
0
∗2
K13
–
K10
∗2
K12
–
∗2
K11
–
∗2
K10
–
KCP13
1
KCP12
1
KCP11
1
KCP10
1
R03HIZ
0
R02HIZ
0
R01HIZ
0
R00HIZ
0
R03
0
R00
R02
0
R01
0
R00
0
1
0
1/2V
V
LCD system voltage regulator power source switch
DD
DD
1/2V
V
Low-speed operation voltage regulator power source switch
DD
DD
On
Off
High-speed operation voltage regulator on/off
V
V
Logic system power source switch
D3
D1L
OSC3
OSC1
CPU clock switch
On
Off
OSC3 oscillation On/Off
Unused
Unused
Unused
SVD criteria voltage setting
[SVDS2–0]
Voltage(V)
1.85/0.98
On
Off
Analog comparator On/Off
+ > -
+ < -
Analog comparator data
Low
Normal
SVD evaluation data
On
Off
SVD circuit On/Off
FOUT output enable
Enable Disable
Stopwatch direct input switch
0: K00=Run/Stop, K01=Lap 1: K00=Lap, K01=Run/Stop
FOUT
frequency
selection
Unused
Unused
Enable
Disable
Watchdog timer enable
Reset
Invalid
Watchdog timer reset (writing)
Enable
Disable
Enable
Disable
K00–K03 interrupt selection register
Enable
Disable
Enable
Disable
High
Low
High
Low
K00–K03 input port data
High
Low
High
Low
K00–K03 input comparison register
Enable
Disable
Enable
Disable
K10–K13 interrupt selection register
Enable
Disable
Enable
Disable
High
Low
High
Low
K10–K13 input port data
High
Low
High
Low
K10–K13 input comparison register
Hi-Z
Output
R03 (FOUTE=0)/FOUT (FOUTE=1) Hi-Z control
Hi-Z
Output
R02 (PTOUT=0)/TOUT (PTOUT=1) Hi-Z control
Hi-Z
Output
R01 Hi-Z control
Hi-Z
Output
R00 Hi-Z control
High
Low
R03 output port data (FOUTE=0) Fix at "1" when FOUT is used.
High
Low
R02 output port data (PTOUT=0) Fix at "1" when TOUT is used.
High
Low
R01 output port data
High
Low
R00 output port data
EPSON
Comment
0
1
2
3
4
2.00
2.15
2.30
2.45
2.60
[FOFQ1, 0]
0
1
Frequency
f
/64
f
OSC1
OSC1
S1C63666 TECHNICAL MANUAL
5
6
7
2.75
2.90
2
3
/8
f
f
OSC1
OSC3
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