Epson S1C63666 Technical Manual page 104

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
Timing chart
The S1C63666 serial interface timing charts are shown in Figures 4.12.4.2 and 4.12.4.3.
SCTRG (W)
SCTRG (R)
SCLK
SIN
8-bit shift register
SOUT
ISIF
SRDY (Slave mode)
SCTRG (W)
SCTRG (R)
SCLK
SIN
8-bit shift register
SOUT
ISIF
SRDY (Slave mode)
Fig. 4.12.4.2 Serial interface timing chart (when synchronous clock is positive polarity SCLK)
SCTRG (W)
SCTRG (R)
SCLK
SIN
8-bit shift register
SOUT
ISIF
SRDY (Slave mode)
SCTRG (W)
SCTRG (R)
SCLK
SIN
8-bit shift register
SOUT
ISIF
SRDY (Slave mode)
Fig. 4.12.4.3 Serial interface timing chart (when synchronous clock is negative polarity SCLK)
94
(a) When SCPS = "1"
(b) When SCPS = "0"
(a) When SCPS = "1"
(b) When SCPS = "0"
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S1C63666 TECHNICAL MANUAL