Lvds Port 1 (Cn8) - Aaeon GENE-APL5 User Manual

Pin Pin Name
6 GND_AUDIO
7 LEFT_OUT
8 GND_AUDIO
9 RIGHT_OUT
10 +5V_AUDIO

2.5.8 LVDS Port 1 (CN8)

*LVDS LCD_PWR can be set to +3.3V or +5V by JP1
Pin Pin Name
1 BKL_ENABLE
2 BKL_CONTROL
3 LCD_PWR
4 GND
5 LVDS_A_CLK-
6 LVDS_A_CLK+
7 LCD_PWR
8 GND
9 LVDS_DA0-
Chapter 2 – Hardware Information
Signal Type
GND
OUT
GND
OUT
PWR
PIN 29 PIN 30
PIN 1 PIN 2
Signal Type
OUT
OUT
PWR
GND
DIFF
DIFF
PWR
GND
DIFF
Signal Level
+5V
Signal Level
+3.3V/+5V
+3.3V/+5V
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