Aaeon GENE-APL5 User Manual page 14

3.5" subcompact board
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4.1
Product CD/DVD ................................................................................................... 84
Appendix A - Watchdog Timer Programming ................................................................... 86
A.1
Watchdog Timer Registers .................................................................................. 87
A.2
Watchdog Sample Program ................................................................................ 88
Appendix B - I/O Information .............................................................................................. 91
B.1
I/O Address Map ................................................................................................... 92
B.2
Memory Address Map ......................................................................................... 94
B.3
IRQ Mapping Chart ............................................................................................... 95
Appendix C - Mating Connectors ..................................................................................... 100
C.1
List of Mating Connectors and Cables ............................................................ 101
Appendix D - Digital I/O Ports .......................................................................................... 103
D.1
Digital I/O Register .............................................................................................. 104
D.2
Digital I/O Sample Code (4 in 4 out, 2 low 2 high) ...................................... 106
Preface
XIV

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