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Aaeon GENE-BT07 User Manual

3.5” subcompact board
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GENE-BT07
3.5" Subcompact Board
st
User's Manual 1
Ed
Last Updated: December 30, 2015

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Summary of Contents for Aaeon GENE-BT07

  • Page 1 GENE-BT07 3.5” Subcompact Board User’s Manual 1 Last Updated: December 30, 2015...

  • Page 2: Copyright Notice

    AAEON assumes no liabilities resulting from errors or omissions in this document, or from the use of the information contained herein. AAEON reserves the right to make changes in the product design without notice to its users.
  • Page 3 Acknowledgement All other products’ name or trademarks are properties of their respective owners. ® Microsoft Windows is a registered trademark of Microsoft Corp.  ® ® ® ® Intel , Pentium , Celeron , and Xeon are registered trademarks of Intel ...
  • Page 4 Before setting up your product, please make sure the following items have been shipped: Item Quantity GENE-BT07  Product CD/DVD with User’s Manual (in pdf) and drivers  If any of these items are missing or damaged, please contact your distributor or sales representative immediately.
  • Page 5 (if any), its specifications, dimensions, jumper/connector settings/definitions, and driver installation instructions (if any), to facilitate users in setting up their product. Users may refer to the AAEON.com for the latest version of this document. Preface...
  • Page 6 Safety Precautions Please read the following safety instructions carefully. It is advised that you keep this manual for future references All cautions and warnings on the device should be noted. Make sure the power source matches the power rating of the device. Position the power cord so that people cannot step on it.
  • Page 7 If any of the following situations arises, please the contact our service personnel: Damaged power cord or plug Liquid intrusion to the device iii. Exposure to moisture Device is not working as expected or in a manner as described in this manual The device is dropped or damaged Any obvious signs of damage displayed on the device...
  • Page 8 FCC Statement This device complies with Part 15 FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received including interference that may cause undesired operation.
  • Page 9 China RoHS Requirements (CN) 产品中有毒有害物质或元素名称及含量 AAEON Main Board/ Daughter Board/ Backplane 有毒有害物质或元素 部件名称 铅 汞 镉 六价铬 多溴联苯 多溴二苯醚 (Pb) (Hg) (Cd) (Cr(VI)) (PBB) (PBDE) 印刷电路板 ○ ○ ○ ○ ○ ○ 及其电子组件 外部信号 ○ ○ ○ ○ ○ ○...
  • Page 10 China RoHS Requirement (EN) Poisonous or Hazardous Substances or Elements in Products AAEON Main Board/ Daughter Board/ Backplane Poisonous or Hazardous Substances or Elements Hexavalent Polybrominated Polybrominated Component Lead Mercury Cadmium Chromium Biphenyls Diphenyl Ethers (Pb) (Hg) (Cd) (Cr(VI)) (PBB) (PBDE) PCB &...

  • Page 11: Table Of Contents

    Table of Contents Chapter 1 - Product Specifications ..................1 Specifications ......................2 Chapter 2 – Hardware Information ..................4 Dimensions ....................... 5 Jumpers and Connectors ..................7 Block Diagram ......................9 List of Jumpers ....................... 10 2.4.1 LVDS Port Backlight Inverter VCC Selection (JP1) ....11 2.4.2 LVDS Port Operating VDD Selection (JP4) .......
  • Page 12 2.5.10 SPI Debug Port (CN19) ..............23 2.5.11 ALS Connector (CN21) (Reserved) ..........24 2.5.12 CPU/SYS Fan Connector (CN24/46) .......... 25 2.5.13 LAN1/2 Connector (CN27/26) ............ 25 2.5.14 eDP Connector (CN29) ..............26 2.5.15 CRT Connector (CN30) ..............27 2.5.16 RTC Battery Connector (CN31) ...........
  • Page 13 Setup submenu: Chipset ..................52 3.5.1 Chipset: Host Bridge ..............53 3.5.1.1 Host Bridge: IGD - LCD Control ........54 3.5.2 Chipset: South Bridge ..............56 3.5.2.1 South Bridge: Azalia HD Audio ........57 3.5.2.2 South Bridge: USB Configuration ........58 3.5.2.3 South Bridge: PCI Express Configuration ......

  • Page 14: Chapter 1 - Product Specifications

    Chapter 1 Chapter 1 - Product Specifications...

  • Page 15: Specifications

    Specifications System 3.5” Form Factor  ® ® Intel Celeron J1900 processor SoC Processor  204-pin DDR3L 1333 SODIMM up to 8 GB System Memory  ® ® Intel Celeron J1900 processor SoC Chipset  RTL8111E, RJ-45 x 2 Ethernet ...
  • Page 16 ® Chipset Intel® Celeron J1900 processor SoC  VGA up to 2560 x 1600 @ 60 Hz Resolution  LVDS up to 1920 x 1200 @ 60 Hz eDP up to 2560 x 1600 @ 60Hz 18/24-bit Dual-Channel LVDS LCD Output Interface ...

  • Page 17: Chapter 2 - Hardware Information

    Chapter 2 Chapter 2 – Hardware Information...

  • Page 18: Dimensions

    Dimensions Component side Component Side Chapter 2 – Hardware Information...
  • Page 19 Solder side Solder Side With optional heat sink optional Chapter 2 – Hardware Information...

  • Page 20: Jumpers And Connectors

    Jumpers and Connectors Component side Component Side Chapter 2 – Hardware Information...
  • Page 21 Solder side Solder Side Chapter 2 – Hardware Information...

  • Page 22: Block Diagram

    Block Diagram Chapter 2 – Hardware Information...

  • Page 23: List Of Jumpers

    List of Jumpers Please refer to the table below for all of the board’s jumpers that you can configure for your application Label Function LVDS port backlight inverter VCC selection LVDS port operating VDD selection COM6 pin8 function selection COM2 pin8 function selection JP10 COM1 pin8 function selection JP11...

  • Page 24: Lvds Port Backlight Inverter Vcc Selection (Jp1)

    2.4.1 LVDS Port Backlight Inverter VCC Selection (JP1) 1 2 3 1 2 3 +12V +5V (Default) 2.4.2 LVDS Port Operating VDD Selection (JP4) 1 2 3 1 2 3 +3.3V (Default) 2.4.3 COM6 Pin8 Function Selection (JP8) Ring(Default) +12V 2.4.4 COM2 Pin8 Function Selection (JP9) +12V Ring(Default)

  • Page 25: Com1 Pin8 Function Selection (Jp10)

    2.4.5 COM1 Pin8 Function Selection (JP10) +12V Ring(Default) 2.4.6 eDP Port Backlight Inverter VCC Selection (JP11) 1 2 3 1 2 3 +12V +5V (Default) 2.4.7 eDP Port Operating VDD Selection (JP13) 1 2 3 1 2 3 +3.3V (Default) 2.4.8 Clear CMOS Jumper (JP21) 1 2 3 1 2 3...

  • Page 26: Front Panel Connector (Jp19) (Reserved, Not Used)

    2.4.9 Front Panel Connector (JP19) (Reserved, not used) Signal Signal PWR_BTN- PWR_BTN+ HDD_LED- HDD_LED+ SPEAKER- SPEAKER+ PWR_LED- PWR_LED+ H/W RESET- H/W RESET+ Chapter 2 – Hardware Information...

  • Page 27: List Of Connectors

    List of Connectors Please refer to the table below for all of the board’s connectors that you can configure for your application Label Function LVDS Back light Control Connector DC 12V Power Input LVDS Connector Audio Connector CN10 mSATA (Half-Mini Card) CN12 COM Port 2 CN14...
  • Page 28 CN34 DDR SO-DOMM socket CN35 SIM socket CN37 Mini Card (Full-Mini Card) CN38 Speaker Left channel CN39 Speaker Right channel CN40 USB Port 1 CN41 USB Port5 from HUB CN42 USB Port6 from HUB CN43 USB Port7 from HUB CN44 USB Port3 from HUB CN45 USB Port3 from HUB...

  • Page 29: Lvds Back Light Control Connector (Cn3)

    2.5.1 LVDS Back light Control Connector (CN3) Pin Name Signal Type Signal Level BKL_PWR +5V / +12V BKL_CONTROL BKL_ENABLE 2.5.2 DC 12V Power Input (CN7) Pin Name Signal Type Signal Level 12 V +12 V Chapter 2 – Hardware Information...

  • Page 30: Lvds Port (Cn8)

    2.5.3 LVDS Port (CN8) PIN 29 PIN 30 PIN 1 PIN 2 * LVDS LCD_PWR can be set to 3.3V or +5V by JP1 * LVDS VDD power can be set by JP4 Pin Name Signal Type Signal Level BKL_ENABLE BKL_CONTROL LCD_PWR +3.3V/+5V...

  • Page 31: Audio I/O Port (Cn9)

    LVDS_DA3+ DIFF DDC_DATA +3.3V DDC_CLK +3.3V LVDS_DB0- DIFF LVDS_DB0+ DIFF LVDS_DB1- DIFF LVDS_DB1+ DIFF LVDS_DB2- DIFF LVDS_DB2+ DIFF LVDS_DB3- DIFF LVDS_DB3+ DIFF LCD_PWR +3.3V/+5V LVDS_B_CLK- DIFF LVDS_B_CLK+ DIFF 2.5.4 Audio I/O Port (CN9) MIC_L MIC_R GND_AUDIO LINE_L_IN LINE_R_IN GND_AUDIO LEFT_OUT GND_AUDIO RIGHT_OUT +5V_AUDIO...

  • Page 32: Msata (Half-Minicard) (Cn10)

    LINE_L_IN LINE_R_IN GND_AUDIO LEFT_OUT GND_AUDIO RIGHT_OUT +5V_AUDIO 2.5.5 mSATA (Half-MiniCard) (CN10) Pin Name Signal Type Signal Level PCIE_WAKE# +3.3VSB +3.3V +1.5V +1.5V PCIE_CLK_REQ# PCIE_REF_CLK- DIFF PCIE_REF_CLK+ DIFF Chapter 2 – Hardware Information...
  • Page 33 W_DISABLE# +3.3V PCIE_RST# +3.3V mSATA_RXP DIFF +3.3VSB +3.3V mSATA_RXN DIFF +1.5V +1.5V SMB_CLK +3.3V mSATA_TXN DIFF SMB_DATA +3.3V mSATA_TXP DIFF +3.3VSB +3.3V +3.3VSB +3.3V Chapter 2 – Hardware Information...

  • Page 34: Com Port 1/2/6 (Cn20/12/32)

    +1.5V +1.5V +3.3VSB +3.3V * CN10 is for mSATA only 2.5.6 COM Port 1/2/6 (CN20/12/32) RI/+5V/+12V * Pin 8 can’t be set by JP8/9/10 RS-232 Pin Name Signal Type Signal Level ± 5V ± 5V Chapter 2 – Hardware Information...

  • Page 35: Com Port 3/4/5 (Cn14/15/28)

    ± 5V RI/+5V/+12V IN/ PWR +5V/+12V 2.5.7 COM Port 3/4/5 (CN14/15/28) Pin Name Signal Type Signal Level ± 9V ± 9V ± 9V 2.5.8 USB Port 0/1 (CN25/40) Chapter 2 – Hardware Information...

  • Page 36: Usb Hub Port 1/2/3/4/5/6/7 (Cn18/17/44/45/41/42/43)

    Pin Name Signal Type Signal Level +5VSB +5 V USB_D- DIFF USB_D+ DIFF 2.5.9 USB Hub Port 1/2/3/4/5/6/7 (CN18/17/44/45/41/42/43) Pin Name Signal Type Signal Level +5VSB +5 V USB_D- DIFF USB_D+ DIFF 2.5.10 SPI Debug Port (CN19) Chapter 2 – Hardware Information...

  • Page 37: Als Connector (Cn21) (Reserved)

    Pin Name Signal Type Signal Level SPI_DATAIN_F SPI_CLK_F +3V3_SPI 3.3 V SPI_DATAOUT_F SPI_CS#_F 2.5.11 ALS Connector (CN21) (Reserved) Pin Name Signal Type Signal Level +3VS_LS I2C_DATA I2C_CLK LS_INT Chapter 2 – Hardware Information...

  • Page 38: Cpu/Sys Fan Connector (Cn24/46)

    2.5.12 CPU/SYS Fan Connector (CN24/46) FAN_TAC FAN_POWER Pin Name Signal Type Signal Level FAN_POWER +12V FAN_TAC 2.5.13 LAN1/2 Connector (CN27/26) ACT/LINK SPEED Pin Name Signal Type Signal Level MDI0+ DIFF MDI0- DIFF MDI1+ DIFF MDI2+ DIFF MDI2- DIFF MDI1- DIFF MDI3+ DIFF MDI3-...

  • Page 39: Edp Connector (Cn29)

    2.5.14 eDP Connector (CN29) PIN 29 PIN 30 PIN 1 PIN 2 Pin Name Signal Type Signal Level BKL_ENABLE BKL_CONTROL LCD_PWR +3.3V/+5V eDP_A_TX3- DIFF eDP_A_TX3+ DIFF LCD_PWR +3.3V/+5V eDP_A_TX2- DIFF eDP_A_TX2+ DIFF eDP_A_TX1- DIFF eDP_A_TX1+ DIFF eDP_A_TX0- DIFF eDP_A_TX0+ DIFF eDP_HPD DIFF eDP_AUX_N...

  • Page 40: Crt Connector (Cn30)

    eDP_AUX_P DIFF +3.3V LCD_PWR +3.3V/+5V * eDP backlight power can be set by JP11 2.5.15 CRT Connector (CN30) Pin Name Signal Type Signal Level GREEN Chapter 2 – Hardware Information...

  • Page 41: Rtc Battery Connector (Cn31)

    BLUE VGA_PWR CRT_PLUG DDC_DAT HSYNC VSYNC DDC_CLK 2.5.16 RTC Battery Connector (CN31) Pin Name Signal Type Signal Level +3.3V 3.3V * Clear CMOS can be set by JP21 2.5.17 SIM card Socket (CN35) Pin Name Signal Type Signal Level Chapter 2 – Hardware Information...

  • Page 42: Minicard Slot (Full Minicard) (Cn37)

    UIM_PWR UIM_RST UIM_CLK UIM_VPP UIM_DATA 2.5.18 MiniCard Slot (Full MiniCard) (CN37) Pin Name Signal Type Signal Level PCIE_WAKE# +3.3VSB +3.3V +1.5V +1.5V PCIE_CLK_REQ# UIM_PWR UIM_DATA PCIE_REF_CLK- DIFF UIM_CLK PCIE_REF_CLK+ DIFF UIM_RST UIM_VPP Chapter 2 – Hardware Information...
  • Page 43 W_DISABLE# +3.3V PCIE_RST# +3.3V PCIE_RX- DIFF +3.3VSB +3.3V PCIE_RX+ DIFF +1.5V +1.5V SMB_CLK +3.3V PCIE_TX- DIFF SMB_DATA +3.3V PCIE_TX+ DIFF USB_D- DIFF USB_D+ DIFF +3.3VSB +3.3V +3.3VSB +3.3V Chapter 2 – Hardware Information...

  • Page 44: Speaker Left Channel (Cn38)

    +1.5V +1.5V +3.3VSB +3.3V 2.5.19 Speaker Left Channel (CN38) Pin Name Signal Type Signal Level SKR_L+ SKR_L- 2.5.20 Speaker Right Channel (CN39) Pin Name Signal Type Signal Level SKR_R+ SKR_R- Chapter 2 – Hardware Information...

  • Page 45: Power Led Connector (5V) (Cn47) (Optional)

    2.5.21 Power LED Connector (5V) (CN47) (Optional) Pin Name Signal Type Signal Level LED Control 2.5.22 Power LED Connector (12V) (CN48) (Optional) Pin Name Signal Type Signal Level +12V Chapter 2 – Hardware Information...

  • Page 46: Chapter 3 - Ami Bios Setup

    Chapter 3 Chapter 3 - AMI BIOS Setup...

  • Page 47: System Test And Initialization

    System Test and Initialization The board uses certain routines to perform testing and initialization. If an error, fatal or non-fatal, is encountered, a few short beeps or an error message will be outputted. The board can usually continue the boot up sequence with non-fatal errors. The system configuration verification routines check the current system configuration against the values stored in the CMOS memory.

  • Page 48: Ami Bios Setup

    AMI BIOS Setup The AMI BIOS ROM has a pre-installed Setup program that allows users to modify basic system configurations, which is stored in the battery-backed CMOS RAM and BIOS NVRAM so that the information is retained when the power is turned off. To enter BIOS Setup, press <Del>...

  • Page 49: Setup Submenu: Main

    Setup submenu: Main Delete Press ‘ ’ Key to enter Setup Chapter 3 – AMI BIOS Setup...

  • Page 50: Setup Submenu: Advanced

    Setup submenu: Advanced Chapter 3 – AMI BIOS Setup...

  • Page 51: Advanced: Power Management

    3.4.1 Advanced: Power Management Options summary: Power Mode ATX Type AT Type Optimal Default, Failsafe Default Select power supply mode Restore AC Power Power Off Loss Power On Optimal Default, Failsafe Default Last State Select AC power state when power is re-applied after a power failure Enable ACPI Auto Enable Configuration...
  • Page 52 Enable Hibernation Enable Optimal Default, Failsafe Default Disable Enables or Disables System ability to Hibernate (OS/S4 Sleep State). This option may be not effective with some OS ACPI Sleep State Suspend Disabled Optimal Default, Failsafe Default S3 only(Suspend to RAM) Select highest ACPI sleep state the System will enter when the Suspend button is pressed Lock Legacy...

  • Page 53: Power Management: S5 Rtc Wake Settings

    3.4.1.1 Power Management: S5 RTC Wake Settings Options summary: Wake system with Fixed Time Enable Optimal Default, Failsafe Default Disable Enable or disable System wake on alarm event. Wake up time is setting by following settings. Wake up day 0-31 Select 0 for daily system wake up 1-31 for which day of the month that you would like the system to wake up Wake up hour...
  • Page 54 Wake system with Dynamic Time Enable Optimal Default, Failsafe Default Disable Enable or disable System wake on alarm event. Wake up time is current time + Increase minutes. Wake up minute increase 1-15 Chapter 3 – AMI BIOS Setup...

  • Page 55: Advanced: Super Io Configuration

    3.4.2 Advanced: Super IO Configuration Chapter 3 – AMI BIOS Setup...

  • Page 56: Super Io Configuration: Serial Port 1 Configuration

    3.4.2.1 Super IO Configuration: Serial Port 1 Configuration Chapter 3 – AMI BIOS Setup...

  • Page 57: Advanced: H/W Monitor

    3.4.3 Advanced: H/W Monitor Chapter 3 – AMI BIOS Setup...

  • Page 58: Advanced: Cpu Configuration

    3.4.4 Advanced: CPU Configuration Options summary: Intel Virtualization Disabled Technology Enabled Optimal Default, Failsafe Default When enabled, a VMM can utilize the additional hardware capabilities provided by Vander pool Technology Chapter 3 – AMI BIOS Setup...

  • Page 59: Cpu Configuration: Socket 0 Cpu Information

    3.4.4.1 CPU Configuration: Socket 0 CPU Information Chapter 3 – AMI BIOS Setup...

  • Page 60: Advanced: Ide Configuration

    3.4.5 Advanced: IDE Configuration Options summary: Serial-ATA(SATA) Enabled Default Disable SATA Speed Support Gen1 Gen2 Default SATA Mode AHCI Default IDE: Configure SATA controllers as legacy IDE AHCI: Configure SATA controllers to operate in AHCI mode Serial-ATA Port 1 Enabled Default Disable Chapter 3 –...
  • Page 61 SATA Port 1 HotPlug Enabled Disable Default Chapter 3 – AMI BIOS Setup...

  • Page 62: Advanced: Csm Configuration

    3.4.6 Advanced: CSM Configuration Options summary: CSM Support Disable Default Enabled Boot option filter UEFI and Legacy Default Legacy only UEFI only Storage & Video Do not launch UEFI Default Legacy Other PCI devices UEFI Default Legacy Chapter 3 – AMI BIOS Setup...

  • Page 63: Advanced: Usb Configuration

    3.4.7 Advanced: USB Configuration Options summary: Legacy USB Support Enabled Optimal Default, Failsafe Default Disabled Auto Enables BIOS Support for Legacy USB Support. When enabled, USB can be functional in legacy environment like DOS. AUTO option disables legacy support if no USB devices are connected USB Mass Storage Driver Disabled Support...
  • Page 64 Type) Floppy Forced FDD Hard Disk CDROM If Auto. USB devices less than 530MB will be emulated as Floppy and remaining as Floppy and remaining as hard drive. Forced FDD option can be used to force a HDD formatted drive to boot as FDD(Ex. ZIP drive) Chapter 3 –...

  • Page 65: Setup Submenu: Chipset

    Setup submenu: Chipset Chapter 3 – AMI BIOS Setup...

  • Page 66: Chipset: Host Bridge

    3.5.1 Chipset: Host Bridge Options summary: Primary Boot Display VBIOS Default Default LVDS Chapter 3 – AMI BIOS Setup...

  • Page 67: Host Bridge: Igd - Lcd Control

    3.5.1.1 Host Bridge: IGD - LCD Control Options summary: LVDS Disabled Default Enabled Enable or Disable LVDS interface Panel Type 640x480 800x480 800x600 1024x600 Default 1024x768 1280x768 1280x1024 1366x768 Chapter 3 – AMI BIOS Setup...
  • Page 68 1440x900 1600x1200 1920x1080 1920x1200 Select panel resolution. Color Depth 18-Bit Default 24-Bit 36-Bit 48-Bit Select color depth of the panel Backlight Type Normal Default Inverted Select Backlight control type. Inverted: Brightest for low PWM duty cycle and low voltage. Normal: Brightest for high PWM duty cycle and high voltage. Backlight Level Default 100%...

  • Page 69: Chipset: South Bridge

    3.5.2 Chipset: South Bridge Chapter 3 – AMI BIOS Setup...

  • Page 70: South Bridge: Azalia Hd Audio

    3.5.2.1 South Bridge: Azalia HD Audio Options summary: Audio Controller Disabled Default Enabled Control Detection of the Azalia device. Disabled = Azalia will be unconditionally disabled. Enabled = Azalia will be unconditionally Enabled. Auto = Azalia will be enabled if present disabled otherwise. Chapter 3 –...

  • Page 71: South Bridge: Usb Configuration

    3.5.2.2 South Bridge: USB Configuration Options summary: XHCI Mode Enabled Disabled Default Auto Smart Auto Mode of operation of XHCI controller USB Per Port Control Enabled Default Disabled Control each of the USB ports (0~3). Enable: Enable USB per port Disable: Use USB port X settings Chapter 3 –...
  • Page 72 USB Port0/1/2/3 Enabled Default Disabled Enable/Disable USB Port0/1/2/3 Chapter 3 – AMI BIOS Setup...

  • Page 73: South Bridge: Pci Express Configuration

    3.5.2.3 South Bridge: PCI Express Configuration Options summary: PCI Express Root Port 0/1/3 Enabled Optimal Default, Failsafe Default Disabled Enabling/Disabling the PCI Express root ports Hot Plug Disabled Default Enabled Enabling/Disabling the PCI Express Hot Plug Speed Auto Default Gen2 Gen1 Configure PCIe Port Speed Chapter 3 –...

  • Page 74: Setup Submenu: Security

    Setup submenu: Security Change User/Administrator Password You can set a User Password once an Administrator Password is set. The password will be required during boot up, or when the user enters the Setup utility. Please Note that a User Password does not provide access to many of the features in the Setup utility.
  • Page 75 Removing the Password Highlight this item and type in the current password. At the next dialog box press Enter to disable password protection. Chapter 3 – AMI BIOS Setup...

  • Page 76: Setup Submenu: Boot

    Setup submenu: Boot Options summary: Launch PXE OpROM Disabled Default Enabled Launch PXE Option Rom Quiet Boot Disabled Enabled Default En/Disables Quiet Boot option Chapter 3 – AMI BIOS Setup...

  • Page 77: Setup Submenu: Exit

    Setup submenu: Exit Chapter 3 – AMI BIOS Setup...

  • Page 78: Chapter 4 - Drivers Installation

    Chapter 4 Chapter 4 – Drivers Installation...

  • Page 79: Product Cd/Dvd

    Product CD/DVD The GENE-BT06 comes with a product DVD that contains all the drivers and utilities you need to setup your product. Insert the DVD and follow the steps in the autorun program to install the drivers. In case the program does not start, follow the sequence below to install the drivers. Step 1 –...
  • Page 80 Step 4 – Install Audio Driver Open the Step 4 - Audio folder and select your OS Open the.exe file in the folder Follow the instructions Drivers will be installed automatically Step 5 – Install MBI Driver (Optional, Windows 8.1/10 only) Open the Step 5 –...
  • Page 81 Step 6 – Install Serial Port Driver (Optional) For Windows 7: Change User Account Control settings to Never notify Reboot and log in as administrator Chapter 4 – Driver Installation...
  • Page 82 Run patch.bat as administrator Chapter 4 – Driver Installation...
  • Page 83 For Windows 8: Open the Apps Screen, right click on the Command Prompt tile and select Run as Administrator To install the driver (patch.bat), you will first have to locate the file in command prompt. To do that, go to the folder in which the file resides by entering cd (file path) eg: if the file is in a folder named abc in c drive, enter cd c:\abc (screenshot for reference only) You are now at the folder where the file is located.
  • Page 84 Reboot after installation completes. To confirm the installation, go to Device Manager, expand the Ports (COM & LPT) tree and double click on any of the COM ports to open its properties. Go to the Driver tab, select Driver Details and click on serial.sys, you should see its provider as Windows (R) Win 7 DDK Provider.
  • Page 85 Chapter 4 – Driver Installation...
  • Page 86 For Windows 10: You will need administrator rights to install the drivers. To get it, first go to Computer Management in Control Panel and double-click on Administrator In the dialog box, uncheck the Account is disabled option to enable administrator account. Chapter 4 –...
  • Page 87 Restart and sign in as the administrator (not password-protected by default) Go back to the Windows 10 Serial Port drivers directory and run patch.bat as administrator. Chapter 4 – Driver Installation...

  • Page 88: Appendix A - Watchdog Timer Programming

    Appendix A Appendix A - Watchdog Timer Programming...

  • Page 89: Watchdog Timer Registers

    A.1 Watchdog Timer Registers Table 1 : Watch dog relative IO address I/O Base Default Value Note Address 0xA00 I/O Base address for Watchdog operation. This address is assigned by SIO LDN7, register 0x60‐0x61. Table 2 : Watchdog relative register table Register Offset BitNum...
  • Page 90 Output Signal 0x05 0: Level Type 1: Pulse Must set this bit to 1 Watchdog 0x05 0: Disable Timer Enable 1: Enable Timeout Status 0x05 1: timeout occurred. Write a 1 to clear timeout status Timer Counter 0x06 Time of watchdog timer (0~255) Appendix A –...

  • Page 91: Watchdog Sample Program

    A.2 Watchdog Sample Program *********************************************************************// WDT I/O operation relative definition (Please reference to Table 1) #define WDTAddr 0xA00 // WDT I/O base address Void WDTWriteByte(byte Register, byte Value); byte WDTReadByte(byte Register); Void WDTSetReg(byte Register, byte Bit, byte Val); // Watch Dog relative definition (Please reference to Table 2) #define DevReg 0x00 // Device configuration register #define WDTRstBit 0x80 // Watchdog WDTRST# (Bit7) #define WDTRstVal 0x80 // Enabled WDTRST#...
  • Page 92 // (boolean)Unit : Select time unit(0: second, 1: minute). AaeonWDTConfig(Counter, Unit); // Procedure : AaeonWDTEnable // This procudure will enable the WDT counting. WDTSetBit(TimerReg, PSWidthBit, PSWidthVal); // Watchdog WDTRST# Enable WDTSetBit(DevReg, WDTRstBit, WDTRstVal); VOID WDTClearTimeoutStatus(){ WDTSetBit(TimerReg, StatusBit, 1); ********************************************************************* ********************************************************************* VOID WDTWriteByte(byte Register, byte Value){ IOWriteByte(WDTAddr+Register, Value);...

  • Page 93: Appendix B - I/O Information

    Appendix B Appendix B - I/O Information...

  • Page 94: I/O Address Map

    I/O Address Map Appendix B – I/O Information...
  • Page 95 Appendix B – I/O Information...

  • Page 96: Memory Address Map

    Memory Address Map Appendix B – I/O Information...

  • Page 97: Irq Mapping Chart

    IRQ Mapping Chart Appendix B – I/O Information...
  • Page 98 Appendix B – I/O Information...
  • Page 99 Appendix B – I/O Information...
  • Page 100 Appendix B – I/O Information...
  • Page 101 Appendix B – I/O Information...
  • Page 102 Appendix B – I/O Information...
  • Page 103 Appendix B – I/O Information...
  • Page 104 Appendix B – I/O Information...
  • Page 105 Appendix B – I/O Information...
  • Page 106 Appendix B – I/O Information...

  • Page 107: Appendix C - Mating Connectors

    Appendix C Appendix C – Mating Connectors...

  • Page 108: List Of Mating Connectors And Cables

    List of Mating Connectors and Cables Mating Connector Connector Available Function Cable P/N Label Cable Vendor Model no CN39 Amplifier Molex 51021-0200 right channel output CN38 Amplifier Molex 51021-0200 left channel output MIC/Line in Molex 51021-1000 Audio Cable 1709100254 LVDS LCD Hirose DF13-30DS -1.25C...
  • Page 109 CN43 USB HUB Molex 51021-0500 USB2.0 1700050207 Port7 Cable connector CN20 COM Port1 Molex 51021-0900 COM Cable 1701090150 Connector CN12 COM Port2 Molex 51021-0900 COM Cable 1701090150 Connector CN14 COM Port3 Molex 51021-0900 COM Cable 1701090150 Connector CN15 COM Port4 Molex 51021-0900 COM Cable...

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