Aaeon GENE-APL5 User Manual
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Aaeon GENE-APL5 User Manual

3.5” subcompact board
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GENE-APL5
3.5" Subcompact Board
User's Manual 5
th
Ed
Last Updated: November 16, 2021

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Summary of Contents for Aaeon GENE-APL5

  • Page 1 GENE-APL5 3.5” Subcompact Board User’s Manual 5 Last Updated: November 16, 2021...
  • Page 2 AAEON assumes no liabilities resulting from errors or omissions in this document, or from the use of the information contained herein. AAEON reserves the right to make changes in the product design without notice to its users.
  • Page 3 Acknowledgements All other products’ name or trademarks are properties of their respective owners. Microsoft Windows is a registered trademark of Microsoft Corp.  Intel® , Pentium® , Celeron® , and Xeon® are registered trademarks of Intel  Corporation Intel Core™ and Intel Atom™ are trademarks of Intel Corporation ...
  • Page 4 Packing List Before setting up your product, please make sure the following items have been shipped: Item Quantity GENE-APL5 MB  Heatsink  If any of these items are missing or damaged, please contact your distributor or sales representative immediately.
  • Page 5 (if any), its specifications, dimensions, jumper/connector settings/definitions, and driver installation instructions (if any), to facilitate users in setting up their product. Users may refer to the product page at AAEON.com for the latest version of this document. Preface...
  • Page 6 Safety Precautions Please read the following safety instructions carefully. It is advised that you keep this manual for future references All cautions and warnings on the device should be noted. Make sure the power source matches the power rating of the device. Position the power cord so that people cannot step on it.
  • Page 7 If any of the following situations arises, please the contact our service personnel: Damaged power cord or plug Liquid intrusion to the device iii. Exposure to moisture Device is not working as expected or in a manner as described in this manual The device is dropped or damaged Any obvious signs of damage displayed on the device...
  • Page 8 FCC Statement This device complies with Part 15 FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received including interference that may cause undesired operation.
  • Page 9 China RoHS Requirements (CN) 产品中有毒有害物质或元素名称及含量 AAEON Main Board/ Daughter Board/ Backplane 有毒有害物质或元素 部件名称 铅 汞 镉 六价铬 多溴联苯 多溴二苯醚 (Pb) (Hg) (Cd) (Cr(VI)) (PBB) (PBDE) 印刷电路板 ○ ○ ○ ○ ○ ○ 及其电子组件 外部信号 ○ ○ ○ ○ ○ ○...
  • Page 10 China RoHS Requirement (EN) Poisonous or Hazardous Substances or Elements in Products AAEON Main Board/ Daughter Board/ Backplane Poisonous or Hazardous Substances or Elements Hexavalent Polybrominated Polybrominated Component Lead Mercury Cadmium Chromium Biphenyls Diphenyl Ethers (Pb) (Hg) (Cd) (Cr(VI)) (PBB) (PBDE) PCB &...

  • Page 11: Table Of Contents

    Table of Contents Chapter 1 - Product Specifications..................1 Specifications ......................2 Function Block Diagram ..................6 Chapter 2 – Hardware Information ..................7 Dimensions ....................... 8 2.1.1 Dimensions (Optional HDMI SKU) ............ 10 Jumpers and Connectors ..................13 2.2.1 Jumpers and Connectors (Optional HDMI SKU)......
  • Page 12 2.4.5 External Power Input (CN5) ............... 25 2.4.6 External +5VSB Input (CN6) (Optional) .......... 26 2.4.7 Audio I/O Port (CN7) ................26 2.4.8 LVDS Port 1 (CN8) ................27 2.4.9 COM Port 2 (CN9) ................29 2.4.10 LPT Port or Digital I/O Port (CN10) ........... 31 2.4.11 LPC Port (CN11) ..................
  • Page 13 2.4.33 Mini-Card Slot (Half-Mini) (CN33) ........... 53 2.4.34 mSATA (Full-Size) (CN34) ..............55 Chapter 3 - AMI BIOS Setup ....................58 System Test and Initialization ................59 AMI BIOS Setup ..................... 60 Setup Submenu: Main ................... 61 Setup Submenu: Advanced ................. 62 3.4.1 Trusted Computing ................
  • Page 14 Setup Submenu: Save & Exit ................89 User Notes ......................90 Chapter 4 – Drivers Installation ..................... 91 Drivers Download and Installation ..............92 Appendix A - I/O Information ....................94 I/O Address Map ....................95 Memory Address Map ..................97 IRQ Mapping Chart ....................

  • Page 15: Chapter 1 - Product Specifications

    Chapter 1 Chapter 1 - Product Specifications...

  • Page 16: Specifications

    Specifications System Form Factor 3.5'' Subcompact Board Intel® Atom™/ Celeron®/ Pentium® Processor: Pentium® N4200 (4C/4T, 1.10GHz, up to 2.50GHz) Celeron® N3350 (2C/2T, 1.10GHz, up to 2.40GHz) Atom® E3950 (4C/4T, 1.60GHz, up to 2.00GHz) Atom® E3940 (4C/4T, 1.60GHz, up to 1.80GHz) Atom®...
  • Page 17 Power Power Requirement +12V (Optional: +9~19V) Power Supply Type AT/ATX Connector Phoenix 2-pin Connector Power Consumption (Typical) 2.03A at +12V with Intel® E3950, DDR3L 1866MHz 8GB memory Power Consumption (Max) 2.45A at +12V with Intel® E3950, DDR3L 1866MHz 8GB memory Display Controller Intel®...
  • Page 18 Internal I/O USB2.0 x 4 Serial Port COM2, COM3 (RS232/422/485, supports 5V/12V/RI) COM4 (RS232, supports RI) Video LVDS1 Dual Channel 18/24-bit x 1 LVDS2 Dual Channel 18/24-bit x 1 (Optional: HDMI 1.4b) SATA SATA III x 1 +5V SATA Power Connector x 1 Audio Audio Header x 1 DIO/GPIO...
  • Page 19 Mechanical Dimensions (L x W) 5.75” x 4” (146mm x 101.7mm) Environment Operating Temperature 32° F ~ 140° F (0° C ~ 60° C) Storage Temperature -40° F ~ 176° F (-40° C ~ 80° C) Operating Humidity 0% ~ 90% relative humidity, non-condensing MTBF (Hours) 365,976 Certification...

  • Page 20: Function Block Diagram

    Function Block Diagram Chapter 1 – Product Specifications...

  • Page 21: Chapter 2 - Hardware Information

    Chapter 2 Chapter 2 – Hardware Information...

  • Page 22: Dimensions

    Dimensions Component Side Chapter 2 – Hardware Information...
  • Page 23 Solder Side Chapter 2 – Hardware Information...

  • Page 24: Dimensions (Optional Hdmi Sku)

    2.1.1 Dimensions (Optional HDMI SKU) Component Side Chapter 2 – Hardware Information...
  • Page 25 Solder Side Chapter 2 – Hardware Information...
  • Page 26 With Heatsink Chapter 2 – Hardware Information...

  • Page 27: Jumpers And Connectors

    Jumpers and Connectors Component Side Component Side >0 ±0. >10 ±0. >50 ±0. >200 ±0. >500 ±0. ANGLE TO ±0.5° Chapter 2 – Hardware Information...
  • Page 28 >0 ±0.1 t=1.8mm SPEC.: DWG No. 1907APL504 >10 ±0.2 >50 ±0.3 NAME PCB_DRAWING FINISH: APPROVED CHECKED DESIGNED >200 ±0.5 >500 ±0.8 GENE-APL5 UNIT: MM MODEL No. Kevin Willie ANGLE TOL. A1.1 SHEET: REV. SCALE: ±0.5° Chapter 2 – Hardware Information...

  • Page 29: Jumpers And Connectors (Optional Hdmi Sku)

    2.2.1 Jumpers and Connectors (Optional HDMI SKU) Component Side Component Side >0 ± >10 ± >50 ± >200 ± >500 ± ANGLE ±0 Chapter 2 – Hardware Information...
  • Page 30 >0 ±0.1 t=1.8mm SPEC.: DWG No. 1907APL504 >10 ±0.2 >50 ±0.3 FINISH: APPROVED CHECKED DESIGNED NAME PCB_DRAWING >200 ±0.5 >500 ±0.8 GENE-APL5 UNIT: MM MODEL No. Kevin Willie ANGLE TOL. A1.1 REV. SHEET: SCALE: ±0.5° Chapter 2 – Hardware Information...

  • Page 31: List Of Jumpers

    List of Jumpers Please refer to the table below for all of the board’s jumpers that you can configure for your application Label Function. LVDS Port1 Backlight Inverter VCC Selection and Operating VDD Selection LVDS Port1 Backlight Lightness Control Mode Selection COM2 Pin8 Function Selection COM3 Pin8 Function Selection Auto Power Button Enable/Disable Selection...

  • Page 32: Lvds Port 1 Operating Vdd Selection (Jp1)

    2.3.2 LVDS Port 1 Operating VDD Selection (JP1) +3.3V (Default) Note: To prevent damage to the system or unwanted operation, do not use any other configuration for JP1 than what is shown in Ch2.4.1 and Ch2.4.2. 2.3.3 LVDS Port 1 Backlight Lightness Control Mode Selection (JP2) 1 2 3 VR Mode (Default) PWM Mode...

  • Page 33: Com3 Pin8 Function Selection (Jp4)

    2.3.5 COM3 Pin8 Function Selection (JP4) +12V Ring (Default) 2.3.6 Auto Power Button Enable/Disable Selection (JP5) 1 2 3 Disable/ ATX Mode Enable/ AT Mode (Default) Note: When disabled, the power button of JP6 (pins 1-2) must be used to power on the system.

  • Page 34: Lvds Port 2 Backlight Inverter Vcc Selection (Jp7)

    2.3.8 LVDS Port 2 Backlight Inverter VCC Selection (JP7) +12V +5V (Default) 2.3.9 LVDS Port 2 Operating VDD Selection (JP7) +3.3V (Default) Note: To prevent damage to the system or unwanted operation, do not use any other configuration for JP1 than what is shown in Ch2.4.1 and Ch2.4.2. 2.3.10 LVDS Port 2 Backlight Lightness Control Mode Selection (JP8) VR Mode (Default)

  • Page 35: Touch Screen 4, 5, 8 Wire Selection (Jp9)

    2.3.11 Touch Screen 4, 5, 8 Wire Selection (JP9) 4/8-Wire Mode (Default) 5-Wire Mode 2.3.12 Clear CMOS Jumper (JP10) 1 2 3 Normal (Default) Clear CMOS Chapter 2 – Hardware Information...

  • Page 36: List Of Connectors

    List of Connectors Please refer to the table below for all of the board’s connectors that you can configure for your application Label Function +5VSB Output w/SMBus LVDS Port1 Inverter / Backlight Connector +5V Output for SATA HDD SATA Port External Power Input External +5VSB Input (Optional) Audio I/O Port...

  • Page 37: 5Vsb Output W/Smbus (Cn1)

    Label Function CN24 LVDS Port2 Inverter / Backlight Connector CN25 USB Ports 0 and 1 CN26 LAN (RJ-45) Port2 CN27 LAN (RJ-45) Port1 CN28 COM Port 1 (D-SUB 9) CN29 HDMI Port (Optional) CN30 Battery CN31 VGA Port CN32 Micro SIM Card Socket CN33 Mini-Card Slot (Half-Size) CN34...

  • Page 38: Lvds Port 1 Inverter / Backlight Connector (Cn2)

    2.4.2 LVDS Port 1 Inverter / Backlight Connector (CN2) Pin Name Signal Type Signal Level BKL_PWR +5V / +12V BKL_CONTROL BKL_ENABLE Note 1: LVDS BKL_PWR can be set to +5V or +12V by JP1. Max current is 2A. Note 2: LVDS BKL_CONTROL can be set by JP2 2.4.3 +5V Output for SATA HDD (CN3) Pin Name...

  • Page 39: Sata Port (Cn4)

    2.4.4 SATA Port (CN4) Pin 1 Pin 7 Pin Name Signal Type Signal Level SATA_TX+ DIFF SATA_TX- DIFF SATA_RX- DIFF SATA_RX+ DIFF 2.4.5 External Power Input (CN5) +12V GND Pin Name Signal Type Signal Level +VIN 9V~19V or 12V Note 1: There are two types of power input, 9V~19V or 12V only, by BOM Change. Note 2: Pin 1 +VIN max current is 8A Chapter 2 –...

  • Page 40: External +5Vsb Input (Cn6) (Optional)

    2.4.6 External +5VSB Input (CN6) (Optional) Pin Name Signal Type Signal Level PS_ON# +5VSB Caution: When using CN6 power connector, ensure the ATX power supply is fully discharged when powering off, or before restarting the system. Discharge time depends on the power supply and can be 3 to 5 seconds or more. 2.4.7 Audio I/O Port (CN7) Pin Name...

  • Page 41: Lvds Port 1 (Cn8)

    Pin Name Signal Type Signal Level LINE_L_IN LINE_R_IN GND_AUDIO LEFT_OUT GND_AUDIO RIGHT_OUT +5V_AUDIO 2.4.8 LVDS Port 1 (CN8) Note 1: LVDS LCD_PWR can be set to +3.3V or +5V by JP1. Max current is 2A. Pin Name Signal Type Signal Level BKL_ENABLE BKL_CONTROL LCD_PWR...
  • Page 42 Pin Name Signal Type Signal Level LCD_PWR +3.3V/+5V LVDS_DA0- DIFF LVDS_DA0+ DIFF LVDS_DA1- DIFF LVDS_DA1+ DIFF LVDS_DA2- DIFF LVDS_DA2+ DIFF LVDS_DA3- DIFF LVDS_DA3+ DIFF DDC_DATA +3.3V DDC_CLK +3.3V LVDS_DB0- DIFF LVDS_DB0+ DIFF LVDS_DB1- DIFF LVDS_DB1+ DIFF LVDS_DB2- DIFF LVDS_DB2+ DIFF LVDS_DB3- DIFF LVDS_DB3+...

  • Page 43: Com Port 2 (Cn9)

    2.4.9 COM Port 2 (CN9) Note 1: Pin 8 mode (Ring/+5V/+12V) can be set by JP3. Max current in power supply mode is 0.5A Note 2: COM2 RS-232/422/485 can be set by BIOS setting. Default is RS-232. RS-232 Mode Pin Name Signal Type Signal Level DCD2...
  • Page 44 RS-485 Mode Pin Name Signal Type Signal Level RS485_ D2- ±5V RS485_D2+ ±5V NC/+5V/+12V +5V/+12V RS-422 Mode Pin Name Signal Type Signal Level RS422_TX2- ±5V RS422_TX2+ ±5V RS422_RX2+ RS422_RX2- NC/+5V/+12V +5V/+12V Chapter 2 – Hardware Information...

  • Page 45: Lpt Port Or Digital I/O Port (Cn10)

    2.4.10 LPT Port or Digital I/O Port (CN10) LPT Port Definitions Note 1: LPT or Digital I/O function can be set by BIOS. Default is Digital I/O. Note 2: +5V input max current 0.5A LPT Mode Pin Name Signal Type Signal Level STROBE# AFD#...
  • Page 46 Pin Name Signal Type Signal Level ACK# BUSY SLCT Digital I/O Mode Note: +5V input max current 0.5A Pin Name Signal Type Signal Level Chapter 2 – Hardware Information...
  • Page 47 Pin Name Signal Type Signal Level DIO0 DIO1 DIO2 DIO3 DIO4 DIO5 DIO6 DIO7 Chapter 2 – Hardware Information...

  • Page 48: Lpc Port (Cn11)

    2.4.11 LPC Port (CN11) LAD0 LAD1 LAD2 LAD3 +3.3V LFRAME# LRESET# LCLK I2C_CLK I2C_DATA SERIRQ Pin Name Signal Type Signal Level LAD0 +3.3V LAD1 +3.3V LAD2 +3.3V LAD3 +3.3V +3.3V +3.3V LFRAME# LRESET# +3.3V LCLK I2C_CLK +3.3V I2C_DATA +3.3V SERIRQ +3.3V Chapter 2 –...

  • Page 49: Com Port 3 (Cn12)

    2.4.12 COM Port 3 (CN12) Note 1: Pin 8 mode (Ring/+5V/+12V) can be set by JP4. Max current in power supply mode is 0.5A Note 2: COM2 RS-232/422/485 can be set by BIOS setting. Default is RS-232. RS-232 Mode Pin Name Signal Type Signal Level DCD3...
  • Page 50 RS-485 Mode Pin Name Signal Type Signal Level RS485_ D3- ±5V RS485_D3+ ±5V NC/+5V/+12V +5V/+12V RS-422 Mode Pin Name Signal Type Signal Level RS422_TX3- ±5V RS422_TX3+ ±5V RS422_RX3+ RS422_RX3- NC/+5V/+12V +5V/+12V Chapter 2 – Hardware Information...

  • Page 51: Bios Debug Port (Cn13)

    2.4.13 BIOS Debug Port (CN13) Pin Name Signal Type Signal Level SPI_MISO SPI_CLK +3.3VSB +3.3V SPI_MOSI SPI_CS Chapter 2 – Hardware Information...

  • Page 52: Com Port 4 (Cn14)

    2.4.14 COM Port 4 (CN14) Pin Name Signal Type Signal Level DCD4 DSR4 RTS4 ±9V ±9V CTS4 DTR4 ±9V Chapter 2 – Hardware Information...

  • Page 53: Ps/2 Keyboard/Mouse Combo Port (Cn15)

    2.4.15 PS/2 Keyboard/Mouse Combo Port (CN15) Pin Name Signal Type Signal Level KB_ DATA KB_CLK +5VSB MS_DATA MS_CLK 2.4.16 USB 2.0 Port 2 (CN16) Pin Name Signal Type Signal Level +5VSB USB_D- DIFF USB_D+ DIFF Chapter 2 – Hardware Information...

  • Page 54: Usb 2.0 Port 3 (Cn17)

    2.4.17 USB 2.0 Port 3 (CN17) Pin Name Signal Type Signal Level +5VSB USB_D- DIFF USB_D+ DIFF 2.4.18 COM Port 1 (CN18) (Wafer, Optional) Pin Name Signal Type Signal Level DCD1 DSR1 RTS1 ±9V Chapter 2 – Hardware Information...

  • Page 55: Usb 2.0 Port 4 (Cn19)

    Pin Name Signal Type Signal Level ±9V CTS1 DTR1 ±9V 2.4.19 USB 2.0 Port 4 (CN19) Pin Name Signal Type Signal Level +5VSB USB_D- DIFF USB_D+ DIFF Chapter 2 – Hardware Information...

  • Page 56: Usb 2.0 Port 5 (Cn20)

    2.4.20 USB 2.0 Port 5 (CN20) Pin Name Signal Type Signal Level +5VSB USB_D- DIFF USB_D+ DIFF 2.4.21 LVDS Port 2 (CN21) Note: LVDS2 LCD_PWR can be set to +3.3V or +5V by JP7. Max current is 2A Pin Name Signal Type Signal Level BKL_ENABLE...
  • Page 57 Pin Name Signal Type Signal Level LCD_PWR +3.3V/+5V LVDS_A_CLK- DIFF LVDS_A_CLK+ DIFF LCD_PWR +3.3V/+5V LVDS_DA0- DIFF LVDS_DA0+ DIFF LVDS_DA1- DIFF LVDS_DA1+ DIFF LVDS_DA2- DIFF LVDS_DA2+ DIFF LVDS_DA3- DIFF LVDS_DA3+ DIFF DDC_DATA +3.3V DDC_CLK +3.3V LVDS_DB0- DIFF LVDS_DB0+ DIFF LVDS_DB1- DIFF LVDS_DB1+ DIFF LVDS_DB2-...

  • Page 58: Touchscreen Connector (Cn22)

    Pin Name Signal Type Signal Level LVDS_B_CLK- DIFF LVDS_B_CLK+ DIFF 2.4.22 Touchscreen Connector (CN22) 8-Wire Mode Pin Name Signal Type Signal Level TOP EXCITE BOTTOM EXCITE LEFT EXCITE RIGHT EXCITE TOP SENSE BOTTOM SENSE LEFT SENSE RIGHT SENSE Chapter 2 – Hardware Information...
  • Page 59 4-Wire Mode Pin Name Signal Type Signal Level BOTTOM LEFT RIGHT 8 Wires 4 Wires 5 Wires 5-Wire Mode UL(Y) BOTTOM UR(H) LEFT LL(L) RIGHT LR(X) SENSE(S) Pin Name Signal Type Signal Level UL(Y) Chapter 2 – Hardware Information...

  • Page 60: Cpu Fan (Cn23, Optional)

    Pin Name Signal Type Signal Level UR(H) LL(L) LR(X) SENSE(S) 2.4.23 CPU Fan (CN23, Optional) FAN_TAC FAN_POWER Pin Name Signal Type Signal Level FAN_POWER +12V FAN_TAC Chapter 2 – Hardware Information...

  • Page 61: Lvds Port 2 Inverter / Backlight Connector (Cn24)

    2.4.24 LVDS Port 2 Inverter / Backlight Connector (CN24) Pin Name Signal Type Signal Level BKL_PWR +5V / +12V BKL_CONTROL BKL_ENABLE Note 1: LVDS2 BKL_PWR can be set to +5V or +12V by JP7 Note 2: LVDS2 BKL_CONTROL can be set by JP8 2.4.25 USB 3.0 Ports 0 and 1 (CN25) Pin Name...

  • Page 62: Lan (Rj-45) Port 2 (Cn26)

    Pin Name Signal Type Signal Level USB_SSRX− DIFF USB_SSRX+ DIFF USB_SSTX− DIFF USB_SSTX+ DIFF +5VSB USB_D- DIFF USB_D+ DIFF USB_SSRX− DIFF USB_SSRX+ DIFF USB_SSTX− DIFF USB_SSTX+ DIFF 2.4.26 LAN (RJ-45) Port 2 (CN26) Pin Name Signal Type Signal Level MDI0+ DIFF MDI0- DIFF...

  • Page 63: Lan (Rj-45) Port 1 (Cn27)

    Pin Name Signal Type Signal Level MDI2- DIFF MDI1- DIFF MDI3+ DIFF MDI3- DIFF 2.4.27 LAN (RJ-45) Port 1 (CN27) Pin Name Signal Type Signal Level MDI0+ DIFF MDI0- DIFF MDI1+ DIFF MDI2+ DIFF MDI2- DIFF MDI1- DIFF MDI3+ DIFF MDI3- DIFF Chapter 2 –...

  • Page 64: Com Port 1 (Cn28, D-Sub 9)

    2.4.28 COM Port 1 (CN28, D-SUB 9) Pin Name Signal Type Signal Level ±9V ±9V ±9V 2.4.29 HDMI Port (CN29, Optional) Pin Name Signal Type Signal Level TMDS_DAT2+ DIFF TMDS_DAT2- DIFF TMDS_DAT1+ DIFF Chapter 2 – Hardware Information...

  • Page 65: Battery (Cn30)

    Pin Name Signal Type Signal Level TMDS_DAT1- DIFF TMDS_DAT0+ DIFF TMDS_DAT0- DIFF TMDS_CLK+ DIFF TMDS_CLK- DIFF DDC_CLK DDC_DATA HPLG_DETECT 2.4.30 Battery (CN30) Pin Name Signal Type Signal Level +3.3V 3.3V Chapter 2 – Hardware Information...

  • Page 66: Vga Port (Cn31)

    2.4.31 VGA Port (CN31) Pin Name Signal Type Signal Level GREEN BLUE RED_GND_RTN GREEN_GND_RTN BLUE_GND_RTN DDC_DATA HSYNC VSYNC DDC_CLK Chapter 2 – Hardware Information...

  • Page 67: Micro Sim Card Socket (Cn32)

    2.4.32 Micro SIM Card Socket (CN32) Pin Name Signal Type Signal Level UIM_PWR UIM_RST UIM_CLK UIM_VPP UIM_DATA 2.4.33 Mini-Card Slot (Half-Mini) (CN33) Pin Name Signal Type Signal Level PCIE_WAKE# +3.3VSB +3.3V +1.5V +1.5V PCIE_CLK_REQ# Chapter 2 – Hardware Information...
  • Page 68 Pin Name Signal Type Signal Level UIM_PWR UIM_DATA PCIE_REF_CLK- DIFF UIM_CLK PCIE_REF_CLK+ DIFF UIM_RST UIM_VPP W_DISABLE# +3.3V PCIE_RST# +3.3V PCIE_RX- DIFF +3.3VSB +3.3V PCIE_RX+ DIFF +1.5V +1.5V SMB_CLK +3.3V PCIE_TX- DIFF SMB_DATA +3.3V PCIE_TX+ DIFF Chapter 2 – Hardware Information...

  • Page 69: Msata (Full-Size) (Cn34)

    Pin Name Signal Type Signal Level USB_D- DIFF USB_D+ DIFF +3.3VSB +3.3V +3.3VSB +3.3V +1.5V +1.5V +3.3VSB +3.3V 2.4.34 mSATA (Full-Size) (CN34) Note: CN34 can be changed to Mini Card by BOM change. Pin Name Signal Type Signal Level +3.3V +3.3V Chapter 2 –...
  • Page 70 Pin Name Signal Type Signal Level +1.5V +1.5V SATA_RX+ DIFF +3.3V +3.3V SATA_RX- DIFF +1.5V +1.5V Chapter 2 – Hardware Information...
  • Page 71 Pin Name Signal Type Signal Level SMB_CLK +3.3V SATA_TX- DIFF SMB_DATA +3.3V SATA_TX+ DIFF +3.3V +3.3V +3.3V +3.3V +1.5V +1.5V +3.3V +3.3V Chapter 2 – Hardware Information...

  • Page 72: Chapter 3 - Ami Bios Setup

    Chapter 3 Chapter 3 - AMI BIOS Setup...

  • Page 73: System Test And Initialization

    System Test and Initialization The system uses certain routines to perform testing and initialization during the boot up sequence. If an error, fatal or non-fatal, is encountered, the module will output a few short beeps or display an error message. The module can usually continue the boot up sequence with non-fatal errors.

  • Page 74: Ami Bios Setup

    AMI BIOS Setup AMI BIOS ROM has a built-in Setup program that allows users to modify the basic system configuration. This type of information is stored in battery-backed CMOS RAM and BIOS NVRAM so that it retains the Setup information when the power is turned off. Entering Setup Power on the computer and press <Del>or <ESC>...

  • Page 75: Setup Submenu: Main

    Setup Submenu: Main Chapter 3 – AMI BIOS Setup...

  • Page 76: Setup Submenu: Advanced

    Setup Submenu: Advanced Chapter 3 – AMI BIOS Setup...

  • Page 77: Trusted Computing

    3.4.1 Trusted Computing Options Summary Security Device Support Disable Enable Optimal Default, Failsafe Default Enables or Disables BIOS support for security device. O.S. will not show Security Device. TCG EFI protocol and INT1A interface will not be available. SHA-1 PCR Bank Disable Enable Optimal Default, Failsafe Default...
  • Page 78 Options Summary Platform Hierarchy Disabled Enabled Optimal Default, Failsafe Default Enable or disable Platform Hierarchy Storage Hierarchy Disabled Enabled Optimal Default, Failsafe Default Enable or Disable Storage Hierarchy Endorsement Disabled Hierarchy Enabled Optimal Default, Failsafe Default Enable or Disable Endorsement Hierarchy TPM2.0 UEFI Spec TCG_1_2 Version...

  • Page 79: Cpu Configuration

    3.4.2 CPU Configuration Options Summary C-States Disabled Enabled Optimal Default, Failsafe Default Enable/Disable C States. EIST™ Disabled Enabled Optimal Default, Failsafe Default Enable/Disable Intel SpeedStep. Turbo Mode Disabled Enabled Optimal Default, Failsafe Default Turbo Mode Power Limit 1 Enable Disabled Optimal Default, Failsafe Default Enabled Enable/Disable Power Limit 1...
  • Page 80 Options Summary Intel Virtualization Disabled Technology Enabled Optimal Default, Failsafe Default When enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology. VT-d Disabled Optimal Default, Failsafe Default Enabled Enable/Disable CPU VT-d Chapter 3 – AMI BIOS Setup...

  • Page 81: Sata Configuration

    3.4.3 SATA Configuration Options Summary Chipset SATA Disabled Enabled Optimal Default, Failsafe Default Enables or Disables the Chipset SATA Controller. The Chipset SATA controller supports the 2 black internal SATA ports (up to 3Gb/s supported per port). SATA GEN SPEED Auto Optimal Default, Failsafe Default GEN1...

  • Page 82: Pci Express Configuration

    3.4.3.1 PCI Express Configuration Chapter 3 – AMI BIOS Setup...
  • Page 83 Options Summary PCIE Slot (CN33) Disabled Enabled Optimal Default, Failsafe Default Control PCIE Slot (CN33) Hot Plug Disabled Optimal Default, Failsafe Default Enabled PCIE Express Hot Plug Enable/Disable PCIe Speed Auto Optimal Default, Failsafe Default Gen 1 Gen 2 Configure PCIe Speed Chapter 3 –...

  • Page 84: Hardware Monitor

    3.4.4 Hardware Monitor Options Summary Smart Fan Disable Enable Optimal Default, Failsafe Default Enables or Disables Smart Fan. Chapter 3 – AMI BIOS Setup...

  • Page 85: Smart Fan Configuration

    3.4.4.1 Smart Fan Configuration Options Summary Fan 1 Smart Fan Manual Duty Mode Control Auto Duty-Cycle Mode Optimal Default, Failsafe Default Smart Fan Mode Select Temperature Source CPU (external) Optimal Default, Failsafe Default System Select the monitored temperature source for this fan. Duty Cycle 1 Temperature 1 Auto fan speed control.

  • Page 86: Sio Configuration

    3.4.5 SIO Configuration Chapter 3 – AMI BIOS Setup...

  • Page 87: Serial Port 1 Configuration

    3.4.5.1 Serial Port 1 Configuration Options Summary Use This Device Disable Enable Optimal Default, Failsafe Default Enable or Disable this Logical Device. Possible: Use Automatic Settings Optimal Default, Failsafe Default IO=3F8h; IRQ=4 IO=2F8h; IRQ=3 Allows user to change Device's Resource settings. New settings will be reflected on This Setup Page after System restarts.

  • Page 88: Serial Port 2 Configuration

    3.4.5.2 Serial Port 2 Configuration Options Summary Use This Device Disable Enable Optimal Default, Failsafe Default Enable or Disable this Logical Device. Possible: Use Automatic Settings Optimal Default, Failsafe Default IO=2F8h; IRQ=3 IO=3F8h; IRQ=4 Allows user to change Device's Resource settings. New settings will be reflected on This Setup Page after System restarts.

  • Page 89: Serial Port 3 Configuration

    3.4.5.3 Serial Port 3 Configuration Options Summary Use This Device Disable Enable Optimal Default, Failsafe Default Enable or Disable this Logical Device. Possible: Use Automatic Settings Optimal Default, Failsafe Default IO=3E8h; IRQ=11 IO=2E8h; IRQ=11 Allows user to change Device's Resource settings. New settings will be reflected on This Setup Page after System restarts.

  • Page 90: Serial Port 4 Configuration

    3.4.5.4 Serial Port 4 Configuration Options Summary Use This Device Disable Enable Optimal Default, Failsafe Default Enable or Disable this Logical Device. Possible: Use Automatic Settings Optimal Default, Failsafe Default IO=2E8h; IRQ=10 IO=3E8h; IRQ=10 Allows user to change Device's Resource settings. New settings will be reflected on This Setup Page after System restarts.

  • Page 91: Parallel Port Configuration

    3.4.5.5 Parallel Port Configuration Options Summary Use This Device Disable Enable Optimal Default, Failsafe Default Enable or Disable this Logical Device. Chapter 3 – AMI BIOS Setup...

  • Page 92: Power Management

    3.4.6 Power Management Options Summary Power Mode ATX Type Optimal Default, Failsafe Default AT Type Select system power mode Power Saving (ERP) Disabled Optimal Default, Failsafe Default Control Enabled Configure power mode for power saving function. Restore AC Power Last State Optimal Default, Failsafe Default Loss Always On...

  • Page 93: Digital Io Port Configuration

    3.4.7 Digital IO Port Configuration Options Summary DIO Port* Output Input Set DIO as Input or Output Output Level High Optimal Default, Failsafe Default Set output level when DIO pin is output Chapter 3 – AMI BIOS Setup...

  • Page 94: Setup Submenu: Chipset

    Setup Submenu: Chipset Chapter 3 – AMI BIOS Setup...

  • Page 95: North Bridge

    3.5.1 North Bridge Chapter 3 – AMI BIOS Setup...

  • Page 96: North Bridge: Lvds Panel Configuration

    3.5.1.1 North Bridge: LVDS Panel Configuration Note: LVDS2 only available for SKU with two LVDS ports Options Summary LVDS Disabled Enabled Optimal Default, Failsafe Default Enable/Disabled this panel. LVDS Panel Type 640x480@60Hz 800x480@60Hz 800x600@60Hz 1024x600@60Hz 1024x768@60Hz Optimal Default, Failsafe Default 1280x768@60Hz 1280x800@60Hz 1280x1024@60Hz...
  • Page 97 Options Summary Select LCD panel used by Internal Graphics Device by selecting the appropriate setup item. Color Depth 18-bit Optimal Default, Failsafe Default 24-bit 36-bit 48-bit Select panel type Backlight Type Normal Optimal Default, Failsafe Default Inverted Select backlight control signal type Backlight Level Optimal Default, Failsafe Default 100%...

  • Page 98: Setup Submenu: Security

    Setup Submenu: Security Change User/Administrator Password You can set an Administrator Password or User Password. An Administrator Password must be set before you can set a User Password. The password will be required during boot up, or when the user enters the Setup utility. A User Password does not provide access to many of the features in the Setup utility.

  • Page 99: Secure Boot

    3.6.1 Secure Boot Options Summary Secure Boot Disabled Optimal Default, Failsafe Default Enabled Secure Boot feature is Active if Secure Boot is Enabled, Platform Key (PK) is enrolled and the System is in User mode. The mode change requires platform reset Secure Boot Mode Custom Optimal Default, Failsafe Default...

  • Page 100: Key Management

    3.6.1.1 Key Management Options Summary Factory Key Provision Disabled Optimal Default, Failsafe Default Enabled Secure Boot feature is Active if Secure Boot is Enabled, Platform Key (PK) is enrolled and the System is in User mode. The mode change requires platform reset Restore Factory Keys Force System to User Mode.
  • Page 101 Options Summary Remove 'UEFI CA' from DB Device Guard ready system must not list 'Microsoft UEFI CA' Certificate in Authorized Signature database (db) Restore DB defaults Restore DB variable to factory defaults Platform Key(PK) Details Export Update Delete Key Exchange Keys Details Export Update...

  • Page 102: Setup Submenu: Boot

    Setup Submenu: Boot Options Summary Quiet Boot Disabled Enabled Optimal Default, Failsafe Default EnableDisable showing boot logo. Monitor Mwait Disable Enabled Auto Optimal Default, Failsafe Default Enable/Disable Monitor Mwait. To install Linux OS, please set this item to disable. Ipv4 PXE Support Disabled Optimal Default, Failsafe Default Enabled...

  • Page 103: Setup Submenu: Save & Exit

    Setup Submenu: Save & Exit Chapter 3 – AMI BIOS Setup...

  • Page 104: User Notes

    User Notes When installing Linux OS, set the Monitor Mwait to Disabled (See Ch. 3.7 Boot) Chapter 3 – AMI BIOS Setup...

  • Page 105: Chapter 4 - Drivers Installation

    Chapter 4 Chapter 4 – Drivers Installation...

  • Page 106: Drivers Download And Installation

    Drivers Download and Installation Drivers for the GENE-APL5 can be downloaded from the product page on the AAEON website by following this link: https://www.aaeon.com/en/p/embedded-single-board-computers-gene-apl5 Download the driver(s) you need and follow the steps below to install them. Step 1 – Install Chipset Drivers Open the Step1 - Chipset folder followed by SetupChipset.exe...
  • Page 107 Step 4 – Install Audio Drivers Open the Step4 - Audio folder followed by 0006-64bit_Win7_Win8_Win81_Win10_R279.exe Follow the instructions Drivers will be installed automatically Step 5 – Install TXE Driver Open the Step5 - TXE folder followed by SetupTXE.exe Follow the instructions Drivers will be installed automatically Step 6 –...

  • Page 108: Appendix A - I/O Information

    Appendix A Appendix A - I/O Information...

  • Page 109: I/O Address Map

    I/O Address Map Appendix A – I/O Information...
  • Page 110 Appendix A – I/O Information...

  • Page 111: A.2 Memory Address Map

    A.2 Memory Address Map Appendix A – I/O Information...

  • Page 112: A.3 Irq Mapping Chart

    A.3 IRQ Mapping Chart Appendix A – I/O Information...
  • Page 113 Appendix A – I/O Information...
  • Page 114 Appendix A – I/O Information...
  • Page 115 Appendix A – I/O Information...
  • Page 116 Appendix A – I/O Information...

  • Page 117: Appendix B - Mating Connectors

    Appendix B Appendix B – Mating Connectors...

  • Page 118: List Of Mating Connectors And Cables

    List of Mating Connectors and Cables The table notes mating connectors and available cables. Mating Connector Connector Available Function Cable P/N Label Cable Vendor Model No External AUX Power and PHR-6 PS_ON# LVDS Port1 Inverter PHR-5 Connector 2 Pins for +5Vout PHR-2 SATA HDD...
  • Page 119 Function Cable P/N Label Cable Vendor Model No LPT or Digital Parallel Port CN10 Molex 51110-2650 1701260200 I/O Connector Cable AAEON LPC CN11 LPC Connector JST SHR-12V-S-B 1703120130 Cable COM Port #3 Serial Port CN12 Molex 51021-0900 1701090150 Connector Cable...
  • Page 120 Mating Connector Connector Available Function Cable P/N Label Cable Vendor Model No LVDS Port1 CN24 Inverter PHR-5 Connector External RTC Battery CN30 Molex 51021-0200 175011301C Connector Cable Appendix B – Electrical Specifications for I/O Ports...

  • Page 121: Appendix C - Electrical Specifications For I/O Ports

    Appendix C Appendix C – Electrical Specifications for I/O Ports...

  • Page 122: Electrical Specifications For I/O Ports

    Electrical Specifications for I/O Ports Connector Signal Name Rate Output Label +5V/1.5A or LVDS Port1 Inverter / Backlight +5V/+12V +12V/1.5A Connector +5V/1A +5V Output for SATA HDD +3.3V/2A or +3.3V/+5V LVDS Port1 +5V/2A +5V/1A or +5V/+12V COM Port 2 +12V/1A CN10 +5V/1A Digital IO Port...

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