Aaeon GENE-APL5 User Manual page 53

*LVDS2 LCD_PWR can be set to +3.3V or +5V by JP7
Pin Pin Name
1 BKL_ENABLE
2 BKL_CONTROL
3 LCD_PWR
4 GND
5 LVDS_A_CLK-
6 LVDS_A_CLK+
7 LCD_PWR
8 GND
9 LVDS_DA0-
10 LVDS_DA0+
11 LVDS_DA1-
12 LVDS_DA1+
13 LVDS_DA2-
14 LVDS_DA2+
15 LVDS_DA3-
16 LVDS_DA3+
17 DDC_DATA
18 DDC_CLK
19 LVDS_DB0-
20 LVDS_DB0+
21 LVDS_DB1-
22 LVDS_DB1+
23 LVDS_DB2-
24 LVDS_DB2+
25 LVDS_DB3-
Chapter 2 – Hardware Information
Signal Type Signal Level
OUT
OUT
PWR +3.3V/+5V
GND
DIFF
DIFF
PWR +3.3V/+5V
GND
DIFF
DIFF
DIFF
DIFF
DIFF
DIFF
DIFF
DIFF
I/O +3.3V
I/O +3.3V
DIFF
DIFF
DIFF
DIFF
DIFF
DIFF
DIFF
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