5Vsb Output W/Smbus (Cn1); Lvds Port 1 Inverter / Backlight Connector (Cn2) - Aaeon GENE-APL5 User Manual

2.5.1 +5VSB Output w/SMBus (CN1)

Pin Pin Name
1 SMB_DATA
2 GND
3 SMB_CLK
4 GND
5 PS_ON#
6 +5VSB

2.5.2 LVDS Port 1 Inverter / Backlight Connector (CN2)

Pin Pin Name
1 BKL_PWR
2 BKL_CONTROL
3 GND
4 GND
5 BKL_ENABLE
* LVDS BKL_PWR can be set to +5V or +12V by JP1
* LVDS BKL_CONTROL can be set by JP2
Chapter 2 – Hardware Information
1 SMB_DATA
GND
SMB_CLK
GND
PS_ON#
+5VSB
6
Signal Type
I/O
GND
I/O
GND
OUT
PWR
1 BLK_PWR
BKL_CONTROL
2
GND
3
GND
4
BKL_ENABLE
5
Signal Type
PWR
OUT
GND
GND
OUT
Signal level
+3.3V
+3.3V
+5V
+5V
Signal level
+5V / +12V
+5V
22