Example 1:
array_dint[0]
1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
Before shift
array_dint[0]
After shift
Example 2:
31
array_dint[0]
1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
31
array_dint[1]
1
input_1
When enabled, the BSR instruction starts at bit 9 in array_dint[0]. The
instruction unloads array_dint[0].0 into the .UL bit, shifts the remaining bits
right, and loads input_1 into array_dint[0].9. The values in the remaining bits
(10...31) are invalid.
When enabled, the BSR instruction starts at bit 25 in array_dint[1]. The
instruction unloads array_dint[0].0 into the .UL bit, shifts the remaining bits
right, and loads input_1 into array_dint[1].25. The values in the remaining bits
(31...26 in dint_array[1]) are invalid. Note how array_dint[1].0 shifts across
words into array_dint[0].31.
These bits shift right
0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
These bits shift right
Rockwell Automation Publication 1756-RM003N-EN-P - October 2011
Array (File)/Shift Instructions (BSL, BSR, FFL, FFU, LFL, LFU)
9 8 7 6 5 4 3 2 1 0
These bits shift right
1
input_1
9 8 7 6 5 4 3 2 1 0
1 0 0 1 1 1 1 0 0 0
Chapter 9
0
.UL bit
0
0
.UL bit
0
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